Chip-Package Co-Design Methodology for Integrated RF Microsystems

The research aims to develop a chip-package co-design methodology using System on a Chip and System on a Package technologies. This is necessary to span multiple domains both in technology and circuitry in integrated RF microsystems. These systems include RF, analog and digital circuits and are sensitive to the constraints imposed by each domain on the other domains and the package. Most systems are currently being designed in CMOS technology and are driven by the requirements of the digital domain. This research will be conducted in three phases. In the first phase of this project, limits of RF circuit performance will be investigated. The constraints of the digital physical design environment on Rf circuit design will also be examined. In the second phase, emerging technologies such as Copper metal layers and deposition of Ferrite material will be studied for RF passive components, and compared with standard Al metal technology. In the third phase, a co-design methodology will be developed for the chip and the package, that includes component optimization, floor planning and routing. The developed methodology will be used on a test bed that will be fabricated and tested.

The RIT collaboration with Georgia Tech brings expertise in microsystems science and engineering together with design, modeling and characterization of electronic packaging. Graduate students and undergraduates will benefit from the breadth of the research collaboration that includes the synthesis of chip design and packaging, and the advances in integrated RF microsystems