HoDoo: Holistic Design of On-chip Interconnects

Project: Research project

Project Details

Description

The integration of multiple cores on the same chip has signaled the beginning of communication-centric, rather than computation-centric systems. Further, technology trends have accentuated the importance of interconnect-conscious design as global wire delays do not scale down as fast as gate delays in new technologies. Consequently, on-chip networks (OCNs), also called Networks-on-Chip (NOCs), are predicted to be a major bottleneck in designing embedded System-on-Chip (SoC) architectures and high performance multicore architectures alike. However, the design of scalable, high performance, energy and thermal efficient and reliable on-chip networks is inherently more complex because of the stringent resource constraints and technology scaling artifacts of OCNs. The proposed research is aimed at developing a holistic design paradigm for exploring the on-chip network design space.

The research addresses three major issues. First, a simulation platform will be developed to understand the interplay between applications, system architecture and on-chip interconnects. Second, design and analysis of high performance, energy and thermal efficient and reliable on-chip interconnects considering the impacts of technology scaling will be investigated.

Third, design of on-chip interconnects using emerging 3D chip technology will be explored. The success of this research is likely to have a significant influence on the design of next generation multicore/SoC architectures and in fostering new research directions in several areas of multicore computing, which is expected to be the predominant design paradigm for future high performance architectures.

StatusFinished
Effective start/end date7/1/076/30/12

Funding

  • National Science Foundation: $630,894.00

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