Offchip Interconnect Signaling Scheme with Near Zero Simultaneous Switching Noise

Project: Research project

Project Details

Description

The objective of this research is to develop a signaling scheme that produces near zero simultaneous switching noise for I/O circuits switching in a package or printed circuit board. In present packages and printed circuit boards, this is caused by the cavity resonances produced between the power and ground planes due to return path discontinuities. The approach is to replace the power planes using transmission lines that are matched at the source, thereby leading to un-interrupted current return paths. This approach can be applied to both 2D and 3D integrated systems.

Intellectual Merit: Today's electronic systems use a low impedance power distribution network. Contrary to this practice, high impedance transmission lines can be used to supply power, thereby eliminating the need for hundreds of capacitors. Using the proposed interconnection topology, it is expected that copper wires in the package would be sufficient to achieve a bandwidth of 1.6TBps or better between multi-core processors and memory.

Broader Impacts: The high-risk, far-reaching approach investigated in this program is beyond the current focus of the electronics industry, and thus lends itself to university-based research and development. The findings from this research and the approaches developed will be integrated into graduate and undergraduate courses. K-12 students and high school teachers are expected to participate in research, which provides engineering exposure and stimulates engineering interest.

StatusFinished
Effective start/end date5/15/105/31/13

Funding

  • National Science Foundation: $360,001.00

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