SGER: Innovative Off-Chip Interconnects for 45-nm and sub-45-nm Node ICs

The objective of this proposal is to design, fabricate, assemble, and test innovative, high risk and high payoff compliant chip to substrate interconnect structures for the 45 nm and sub-45nm node ICs. To accomplish the goals of this proposal the will fabricate the compliant interconnects using LIGA-like process consisting of sequential plating and photolithography. The PI will design the interconnects to optimize the directional mechanical compliance, electrical resistance, inductance, capacitance, discontinuity between the chip and substrate, minimum temperature increase due to joule heating, and reliability against fatigue failure. The PI will have appropriate prototype test vehicles to test many of his suggested parameters

This proposal supports one of the major challenges in the IC design and fabrication in terms of size, performance, cost, and reliability. This proposal represents fundamental paradigm shift in chip-to-substrate interconnect technology and presents an innovative approach to meet the semiconductor packaging for 2013 and beyond. The broader impact: This proposal will benefit the semiconductor industry of the future in the development of novel innovative technology and could have significant economic impact. It will help train the graduate students in this technology. If this technology is successful, then it will not only help large-scale device applications but in the development of system in a package, which requires careful and cost effective interconnects.