10-Bit Flash ADCs and Beyond: An Automated Framework for TIQ Flash ADCs Design

In this work we introduce the flash ADC design automation (FADA) framework. It aims to reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes the selected TIQ comparators of the flash ADC for differential nonlinearity (DNL), integral nonlinearity (INL), analog voltage range, power consumption and comparator noise values. We performed a survey study on flash ADCs published in the last two decades and compared them to our 10-bit single-channel TIQ flash ADC. Further, it took FADA < 6 h to design the 10-bit TIQ flash ADC compared to few weeks of manual design. Accordingly, FADA selected TIQ comparators set for the 10-bit TIQ flash ADC with DNL and INL values less than 0.17 LSB and 0.16 LSB, respectively, when designed in the ibm65n CMOS technology. The 10-bit TIQ flash ADC has simulated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) values of 57.2 dBs and 61 dBs, respectively. It consumes 1.67 mW of power and operates at 1.57 GSample/s. FADA provides TIQ models to optimize for high-performance versus low-noise TIQ flash ADCs designs.