15-nm channel length MoS2 FETs with single- and double-gate structures

A. Nourbakhsh; A. Zubair; S. Huang; X. Ling; M. S. Dresselhaus; J. Kong; S. De Gendt; T. Palacios

doi:10.1109/VLSIT.2015.7223690

15-nm channel length MoS₂ FETs with single- and double-gate structures

A. Nourbakhsh, A. Zubair, S. Huang, X. Ling, M. S. Dresselhaus, J. Kong, S. De Gendt, T. Palacios

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

32 Scopus citations

Abstract

We demonstrate single- and double-gated (SG & DG) field effect transistors (FETs) with a record source-drain length (L_S/D) of 15 nm built on monolayer (t_ch∼0.7 nm) and 4-layer (t_ch∼3 nm) MoS₂ channels using monolayer graphene as the Source/Drain contacts. The best devices, corresponding to DG 4-layer MoS₂-FETs with L_S/D=15 nm, had an I_on/I_off in excess of 10⁶ and a minimum subthreshold swing (SS_min.) of 90 mV/dec. at V_DS=0.5 V. At L_S/D=1 μm and V_DS=0.5 V, SS_min.=66 mV/dec., which is the best SS reported in MoS₂ FETs, indicating the high quality of the interface and the enhanced channel electrostatics.

Original language	English (US)
Title of host publication	2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	T28-T29
ISBN (Electronic)	9784863485013
DOIs	https://doi.org/10.1109/VLSIT.2015.7223690
State	Published - Aug 25 2015
Event	Symposium on VLSI Technology, VLSI Technology 2015 - Kyoto, Japan Duration: Jun 16 2015 → Jun 18 2015

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2015-August
ISSN (Print)	0743-1562

Other

Other	Symposium on VLSI Technology, VLSI Technology 2015
Country/Territory	Japan
City	Kyoto
Period	6/16/15 → 6/18/15

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.2015.7223690

Cite this

Nourbakhsh, A., Zubair, A., Huang, S., Ling, X., Dresselhaus, M. S., Kong, J., De Gendt, S., & Palacios, T. (2015). 15-nm channel length MoS₂ FETs with single- and double-gate structures. In 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers (pp. T28-T29). Article 7223690 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2015.7223690

@inproceedings{878d0ad11ed44c35a40c4c5285f57958,

title = "15-nm channel length MoS2 FETs with single- and double-gate structures",

abstract = "We demonstrate single- and double-gated (SG & DG) field effect transistors (FETs) with a record source-drain length (LS/D) of 15 nm built on monolayer (tch∼0.7 nm) and 4-layer (tch∼3 nm) MoS2 channels using monolayer graphene as the Source/Drain contacts. The best devices, corresponding to DG 4-layer MoS2-FETs with LS/D=15 nm, had an Ion/Ioff in excess of 106 and a minimum subthreshold swing (SSmin.) of 90 mV/dec. at VDS=0.5 V. At LS/D=1 μm and VDS=0.5 V, SSmin.=66 mV/dec., which is the best SS reported in MoS2 FETs, indicating the high quality of the interface and the enhanced channel electrostatics.",

author = "A. Nourbakhsh and A. Zubair and S. Huang and X. Ling and Dresselhaus, {M. S.} and J. Kong and {De Gendt}, S. and T. Palacios",

note = "Publisher Copyright: {\textcopyright} 2015 JSAP.; Symposium on VLSI Technology, VLSI Technology 2015 ; Conference date: 16-06-2015 Through 18-06-2015",

year = "2015",

month = aug,

day = "25",

doi = "10.1109/VLSIT.2015.7223690",

language = "English (US)",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "T28--T29",

booktitle = "2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers",

address = "United States",

}

Nourbakhsh, A, Zubair, A, Huang, S, Ling, X, Dresselhaus, MS, Kong, J, De Gendt, S & Palacios, T 2015, 15-nm channel length MoS₂ FETs with single- and double-gate structures. in 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers., 7223690, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. T28-T29, Symposium on VLSI Technology, VLSI Technology 2015, Kyoto, Japan, 6/16/15. https://doi.org/10.1109/VLSIT.2015.7223690

15-nm channel length MoS₂ FETs with single- and double-gate structures. / Nourbakhsh, A.; Zubair, A.; Huang, S. et al.
2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. T28-T29 7223690 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - 15-nm channel length MoS2 FETs with single- and double-gate structures

AU - Nourbakhsh, A.

AU - Zubair, A.

AU - Huang, S.

AU - Ling, X.

AU - Dresselhaus, M. S.

AU - Kong, J.

AU - De Gendt, S.

AU - Palacios, T.

PY - 2015/8/25

Y1 - 2015/8/25

N2 - We demonstrate single- and double-gated (SG & DG) field effect transistors (FETs) with a record source-drain length (LS/D) of 15 nm built on monolayer (tch∼0.7 nm) and 4-layer (tch∼3 nm) MoS2 channels using monolayer graphene as the Source/Drain contacts. The best devices, corresponding to DG 4-layer MoS2-FETs with LS/D=15 nm, had an Ion/Ioff in excess of 106 and a minimum subthreshold swing (SSmin.) of 90 mV/dec. at VDS=0.5 V. At LS/D=1 μm and VDS=0.5 V, SSmin.=66 mV/dec., which is the best SS reported in MoS2 FETs, indicating the high quality of the interface and the enhanced channel electrostatics.

AB - We demonstrate single- and double-gated (SG & DG) field effect transistors (FETs) with a record source-drain length (LS/D) of 15 nm built on monolayer (tch∼0.7 nm) and 4-layer (tch∼3 nm) MoS2 channels using monolayer graphene as the Source/Drain contacts. The best devices, corresponding to DG 4-layer MoS2-FETs with LS/D=15 nm, had an Ion/Ioff in excess of 106 and a minimum subthreshold swing (SSmin.) of 90 mV/dec. at VDS=0.5 V. At LS/D=1 μm and VDS=0.5 V, SSmin.=66 mV/dec., which is the best SS reported in MoS2 FETs, indicating the high quality of the interface and the enhanced channel electrostatics.

UR - http://www.scopus.com/inward/record.url?scp=84951083292&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84951083292&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2015.7223690

DO - 10.1109/VLSIT.2015.7223690

M3 - Conference contribution

AN - SCOPUS:84951083292

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - T28-T29

BT - 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - Symposium on VLSI Technology, VLSI Technology 2015

Y2 - 16 June 2015 through 18 June 2015

ER -

Nourbakhsh A, Zubair A, Huang S, Ling X, Dresselhaus MS, Kong J et al. 15-nm channel length MoS₂ FETs with single- and double-gate structures. In 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. T28-T29. 7223690. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2015.7223690