2-D Strain FET (2D-SFET) Based SRAMs - Part I: Device-Circuit Interactions

In this article, we analyze the characteristics of a recently conceived steep switching device 2-D Strain FET (2D-SFET) and present its circuit implications in the context of 6T-SRAM. We discuss the dependence of 2D-SFET characteristics on key design parameters, showing up to $2.7\times $ larger ON-current and 35% decrease in subthreshold swing when compared to 2D-FET. We analyze the performance of 2D-SFET (as drop-in replacement for standard 2D-FET) in 6T-SRAM for a range of design parameters and compare those to 2D-FET 6T-SRAM. 2D-SFET 6T-SRAM achieves up to 5.7% lower access time, 63% higher write margin, and comparable hold margin, but at the cost of comparable to 11% lower read stability and 16% increase in write time. In Part II of this article, we mitigate the read stability issues of 2D-SFET SRAMs by proposing ${V}_{{\mathrm {B}}}$ -enabled SRAM designs.