@inproceedings{0cf7562eeac94814889544a85f17d2e6,
title = "24-bit significand multiplier for FPGA floating-point multiplication",
abstract = "This paper presents a 24-bit significand multiplier for single-precision floating-point multiplication that is optimized for Xilinx FPGAs with 6-input LUTs. The design combines a 24 × 7 LUT-based multiplier and one embedded multiplier to implement a 24 × 24 unsigned multiplier. The proposed design uses 35% fewer LUTs and is 1.11 times faster than a LogiCORE multiplier that also uses one embedded multiplier. A truncated- matrix version that allows faithful rounding uses 78% fewer LUTs and is 1.17 times faster than a LogiCORE multiplier that uses one embedded multiplier. Both designs are comparable in speed to a LogiCORE multiplier that uses two embedded multipliers.",
author = "Walters, {E. George}",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.; 49th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 ; Conference date: 08-11-2015 Through 11-11-2015",
year = "2016",
month = feb,
day = "26",
doi = "10.1109/ACSSC.2015.7421227",
language = "English (US)",
series = "Conference Record - Asilomar Conference on Signals, Systems and Computers",
publisher = "IEEE Computer Society",
pages = "717--721",
editor = "Matthews, {Michael B.}",
booktitle = "Conference Record of the 49th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015",
address = "United States",
}