TY - GEN
T1 - 3D Path finder methodology for the design of 3DICs and interposers
AU - Swaminathan, Madhavan
AU - Martin, Bill
AU - Han, Ki Jin
PY - 2013
Y1 - 2013
N2 - 3D technology is emerging as a mechanism to continue Moore's Law for 3D ICs. Similarly, interposer technology is being viewed as a method to continue 'More than Moore' scaling. With both these technologies providing significantly improved integration levels as compared to other options, the electronics industry is preparing itself for the next semiconductor revolution. With 3D technology still in its infancy, we introduce the concept of path finding in this paper, which is an exploratory phase in the design cycle where early decisions can be made on the technologies to use, the structures to design and the process parameters to define to obtain the appropriate responses. This paper covers the 3D Path Finder (3DPF) methodology which includes model development (user interface) and numerical solver. One example is covered to show the attractiveness of using an exploratory tool such as 3DPF early in the design cycle.
AB - 3D technology is emerging as a mechanism to continue Moore's Law for 3D ICs. Similarly, interposer technology is being viewed as a method to continue 'More than Moore' scaling. With both these technologies providing significantly improved integration levels as compared to other options, the electronics industry is preparing itself for the next semiconductor revolution. With 3D technology still in its infancy, we introduce the concept of path finding in this paper, which is an exploratory phase in the design cycle where early decisions can be made on the technologies to use, the structures to design and the process parameters to define to obtain the appropriate responses. This paper covers the 3D Path Finder (3DPF) methodology which includes model development (user interface) and numerical solver. One example is covered to show the attractiveness of using an exploratory tool such as 3DPF early in the design cycle.
UR - http://www.scopus.com/inward/record.url?scp=84894221479&partnerID=8YFLogxK
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U2 - 10.1109/EDAPS.2013.6724447
DO - 10.1109/EDAPS.2013.6724447
M3 - Conference contribution
AN - SCOPUS:84894221479
SN - 9781479923113
T3 - EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
SP - 21
EP - 24
BT - EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
T2 - 2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013
Y2 - 12 December 2013 through 15 December 2013
ER -