Abstract
A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flash ADC can be applied to low supply voltage. A fat tree encoder that has signal delay of O(log2N] is used for performance. A 6-bit and an 8-bit flash ADC were designed with 0.07 μm CMOS technology and 0.7 V power supply voltage. The 6-bit ADC operates up to 4.76 giga samples per second (GSPS) with 11.35 mW power consumption. In case of the 8-bit ADC, it consumes 48.90 mW at its high speed 3.57 GSPS.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 56-59 |
| Number of pages | 4 |
| Journal | Proceedings of the IEEE Great Lakes Symposium on VLSI |
| State | Published - 2003 |
| Event | Proceedings of the 2003 ACM Great Lakes Symposium on VLSI - Washington, DC, United States Duration: Apr 28 2003 → Apr 29 2003 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering