A 0.07 μm CMOS flash analog-to-digital converter for high speed and low voltage applications

Jincheol Yoo; Kyusun Choi; Jahan Ghaznavi

A 0.07 μm CMOS flash analog-to-digital converter for high speed and low voltage applications

Jincheol Yoo
, Kyusun Choi
, Jahan Ghaznavi

Computer Science and Engineering

Research output: Contribution to journal › Conference article › peer-review

7 Scopus citations

Abstract

A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flash ADC can be applied to low supply voltage. A fat tree encoder that has signal delay of O(log₂N] is used for performance. A 6-bit and an 8-bit flash ADC were designed with 0.07 μm CMOS technology and 0.7 V power supply voltage. The 6-bit ADC operates up to 4.76 giga samples per second (GSPS) with 11.35 mW power consumption. In case of the 8-bit ADC, it consumes 48.90 mW at its high speed 3.57 GSPS.

Original language	English (US)
Pages (from-to)	56-59
Number of pages	4
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
State	Published - 2003
Event	Proceedings of the 2003 ACM Great Lakes Symposium on VLSI - Washington, DC, United States Duration: Apr 28 2003 → Apr 29 2003

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

@article{654ff28ad7c946c0ac49ae663ac3ce27,

title = "A 0.07 μm CMOS flash analog-to-digital converter for high speed and low voltage applications",

abstract = "A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flash ADC can be applied to low supply voltage. A fat tree encoder that has signal delay of O(log2N] is used for performance. A 6-bit and an 8-bit flash ADC were designed with 0.07 μm CMOS technology and 0.7 V power supply voltage. The 6-bit ADC operates up to 4.76 giga samples per second (GSPS) with 11.35 mW power consumption. In case of the 8-bit ADC, it consumes 48.90 mW at its high speed 3.57 GSPS.",

author = "Jincheol Yoo and Kyusun Choi and Jahan Ghaznavi",

year = "2003",

language = "English (US)",

pages = "56--59",

journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

issn = "1066-1395",

publisher = "IEEE Computer Society",

note = "Proceedings of the 2003 ACM Great Lakes Symposium on VLSI ; Conference date: 28-04-2003 Through 29-04-2003",

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TY - JOUR

T1 - A 0.07 μm CMOS flash analog-to-digital converter for high speed and low voltage applications

AU - Yoo, Jincheol

AU - Choi, Kyusun

AU - Ghaznavi, Jahan

PY - 2003

Y1 - 2003

N2 - A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flash ADC can be applied to low supply voltage. A fat tree encoder that has signal delay of O(log2N] is used for performance. A 6-bit and an 8-bit flash ADC were designed with 0.07 μm CMOS technology and 0.7 V power supply voltage. The 6-bit ADC operates up to 4.76 giga samples per second (GSPS) with 11.35 mW power consumption. In case of the 8-bit ADC, it consumes 48.90 mW at its high speed 3.57 GSPS.

AB - A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flash ADC can be applied to low supply voltage. A fat tree encoder that has signal delay of O(log2N] is used for performance. A 6-bit and an 8-bit flash ADC were designed with 0.07 μm CMOS technology and 0.7 V power supply voltage. The 6-bit ADC operates up to 4.76 giga samples per second (GSPS) with 11.35 mW power consumption. In case of the 8-bit ADC, it consumes 48.90 mW at its high speed 3.57 GSPS.

UR - https://www.scopus.com/pages/publications/0038375813

UR - https://www.scopus.com/pages/publications/0038375813#tab=citedBy

M3 - Conference article

AN - SCOPUS:0038375813

SN - 1066-1395

SP - 56

EP - 59

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

T2 - Proceedings of the 2003 ACM Great Lakes Symposium on VLSI

Y2 - 28 April 2003 through 29 April 2003

ER -

A 0.07 μm CMOS flash analog-to-digital converter for high speed and low voltage applications

Abstract

All Science Journal Classification (ASJC) codes

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