A 1 Gb 2 GHz 128 GB/s bandwidth embedded DRAM in 22 nm tri-gate CMOS technology

Fatih Hamzaoglu; Umut Arslan; Nabhendra Bisnik; Swaroop Ghosh; Manoj B. Lal; Nick Lindert; Mesut Meterelliyoz; Randy B. Osborne; Joodong Park; Shigeki Tomishima; Yih Wang; Kevin Zhang

doi:10.1109/JSSC.2014.2353793

A 1 Gb 2 GHz 128 GB/s bandwidth embedded DRAM in 22 nm tri-gate CMOS technology

Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang

Electrical Engineering

Research output: Contribution to journal › Article › peer-review

23 Scopus citations

Abstract

An embedded DRAM (eDRAM) integrated into 22 nm CMOS logic technology using tri-gate high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed, which includes fully integrated programmable charge pumps to over-and underdrive wordlines with output voltage regulation. The die area is 77 mm² and provides 64 GB/s Read and 64 GB/s Write at 1.05 V. 100 μs retention time is achieved at 95°C using the worst case memory array stress patterns. The 1 Gb eDRAM die is multi-chip-packaged with Haswell family Iris Pro™ die to achieve a high-end graphics part, which provides up to 75% performance improvement in silicon, across a wide range of workloads.

Original language	English (US)
Article number	6912029
Pages (from-to)	150-157
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	50
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2014.2353793
State	Published - Jan 1 2015

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/JSSC.2014.2353793

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title = "A 1 Gb 2 GHz 128 GB/s bandwidth embedded DRAM in 22 nm tri-gate CMOS technology",

abstract = "An embedded DRAM (eDRAM) integrated into 22 nm CMOS logic technology using tri-gate high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed, which includes fully integrated programmable charge pumps to over-and underdrive wordlines with output voltage regulation. The die area is 77 mm2 and provides 64 GB/s Read and 64 GB/s Write at 1.05 V. 100 μs retention time is achieved at 95°C using the worst case memory array stress patterns. The 1 Gb eDRAM die is multi-chip-packaged with Haswell family Iris Pro{\texttrademark} die to achieve a high-end graphics part, which provides up to 75% performance improvement in silicon, across a wide range of workloads.",

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AU - Bisnik, Nabhendra

AU - Ghosh, Swaroop

AU - Lal, Manoj B.

AU - Lindert, Nick

AU - Meterelliyoz, Mesut

AU - Osborne, Randy B.

AU - Park, Joodong

AU - Tomishima, Shigeki

AU - Wang, Yih

AU - Zhang, Kevin

PY - 2015/1/1

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AB - An embedded DRAM (eDRAM) integrated into 22 nm CMOS logic technology using tri-gate high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed, which includes fully integrated programmable charge pumps to over-and underdrive wordlines with output voltage regulation. The die area is 77 mm2 and provides 64 GB/s Read and 64 GB/s Write at 1.05 V. 100 μs retention time is achieved at 95°C using the worst case memory array stress patterns. The 1 Gb eDRAM die is multi-chip-packaged with Haswell family Iris Pro™ die to achieve a high-end graphics part, which provides up to 75% performance improvement in silicon, across a wide range of workloads.

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A 1 Gb 2 GHz 128 GB/s bandwidth embedded DRAM in 22 nm tri-gate CMOS technology

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