A 18.87-24.19 GHz VCO with 90-164 kHz 1/f3 Noise Corner and 189.6 dBc/Hz Peak FoM

Harikrishna Kambham; Praful Mankar; Syed Azeemuddin

doi:10.1109/MWSCAS53549.2025.11244498

A 18.87-24.19 GHz VCO with 90-164 kHz 1/f³ Noise Corner and 189.6 dBc/Hz Peak FoM

Harikrishna Kambham
, Praful Mankar
, Syed Azeemuddin

School of Engineering (Behrend)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents an 18.87-24.19 GHz dual-core, dual-mode voltage-controlled oscillator (VCO) using a multi-tap (MT) inductor-based 2-port resonator with capacitive coupling via a mode-switching block. The 2 -port resonator introduces a gate-to-drain phase shift, suppressing flicker phase noise (PN), while the high-quality factor of the tank minimizes thermal PN. The mode-switching block enables dual resonance modes - high-frequency band (HB) and low-frequency band (LB), achieving a wide frequency tuning range (FTR) and low PN in both the 1/f² and 1/f³ regions. The proposed VCO is implemented in 65 nm CMOS, and post-layout results show a PN of -68.7 dBc/Hz at a 10 kHz offset and -118.2 dBc/Hz at a 1 MHz offset from an 18.87 GHz carrier frequency, with a power consumption of 25.65 mW and an area of 0.154 mm². The peak figure of merit (FoM) is 189.6 dBc/ Hz, and the maximum 1/f³ noise corner frequency is 347 kHz across the FTR.

Original language	English (US)
Title of host publication	2025 IEEE 68th International Midwest Symposium on Circuits and Systems, MWSCAS 2025
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	941-945
Number of pages	5
ISBN (Electronic)	9798331589349
DOIs	https://doi.org/10.1109/MWSCAS53549.2025.11244498
State	Published - 2025
Event	68th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2025 - Lansing/E. Lansing, United States Duration: Aug 10 2025 → Aug 13 2025

Publication series

Name	Midwest Symposium on Circuits and Systems
ISSN (Print)	1548-3746
ISSN (Electronic)	1558-3899

Conference

Conference	68th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2025
Country/Territory	United States
City	Lansing/E. Lansing
Period	8/10/25 → 8/13/25

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/MWSCAS53549.2025.11244498

Cite this

Kambham, H., Mankar, P., & Azeemuddin, S. (2025). A 18.87-24.19 GHz VCO with 90-164 kHz 1/f³ Noise Corner and 189.6 dBc/Hz Peak FoM. In 2025 IEEE 68th International Midwest Symposium on Circuits and Systems, MWSCAS 2025 (pp. 941-945). (Midwest Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS53549.2025.11244498

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title = "A 18.87-24.19 GHz VCO with 90-164 kHz 1/f3 Noise Corner and 189.6 dBc/Hz Peak FoM",

abstract = "This paper presents an 18.87-24.19 GHz dual-core, dual-mode voltage-controlled oscillator (VCO) using a multi-tap (MT) inductor-based 2-port resonator with capacitive coupling via a mode-switching block. The 2 -port resonator introduces a gate-to-drain phase shift, suppressing flicker phase noise (PN), while the high-quality factor of the tank minimizes thermal PN. The mode-switching block enables dual resonance modes - high-frequency band (HB) and low-frequency band (LB), achieving a wide frequency tuning range (FTR) and low PN in both the 1/f2 and 1/f3 regions. The proposed VCO is implemented in 65 nm CMOS, and post-layout results show a PN of -68.7 dBc/Hz at a 10 kHz offset and -118.2 dBc/Hz at a 1 MHz offset from an 18.87 GHz carrier frequency, with a power consumption of 25.65 mW and an area of 0.154 mm2. The peak figure of merit (FoM) is 189.6 dBc/ Hz, and the maximum 1/f3 noise corner frequency is 347 kHz across the FTR.",

author = "Harikrishna Kambham and Praful Mankar and Syed Azeemuddin",

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Kambham, H, Mankar, P & Azeemuddin, S 2025, A 18.87-24.19 GHz VCO with 90-164 kHz 1/f³ Noise Corner and 189.6 dBc/Hz Peak FoM. in 2025 IEEE 68th International Midwest Symposium on Circuits and Systems, MWSCAS 2025. Midwest Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 941-945, 68th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2025, Lansing/E. Lansing, United States, 8/10/25. https://doi.org/10.1109/MWSCAS53549.2025.11244498

A 18.87-24.19 GHz VCO with 90-164 kHz 1/f³ Noise Corner and 189.6 dBc/Hz Peak FoM. / Kambham, Harikrishna; Mankar, Praful; Azeemuddin, Syed.
2025 IEEE 68th International Midwest Symposium on Circuits and Systems, MWSCAS 2025. Institute of Electrical and Electronics Engineers Inc., 2025. p. 941-945 (Midwest Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - A 18.87-24.19 GHz VCO with 90-164 kHz 1/f3 Noise Corner and 189.6 dBc/Hz Peak FoM

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AU - Mankar, Praful

AU - Azeemuddin, Syed

PY - 2025

Y1 - 2025

N2 - This paper presents an 18.87-24.19 GHz dual-core, dual-mode voltage-controlled oscillator (VCO) using a multi-tap (MT) inductor-based 2-port resonator with capacitive coupling via a mode-switching block. The 2 -port resonator introduces a gate-to-drain phase shift, suppressing flicker phase noise (PN), while the high-quality factor of the tank minimizes thermal PN. The mode-switching block enables dual resonance modes - high-frequency band (HB) and low-frequency band (LB), achieving a wide frequency tuning range (FTR) and low PN in both the 1/f2 and 1/f3 regions. The proposed VCO is implemented in 65 nm CMOS, and post-layout results show a PN of -68.7 dBc/Hz at a 10 kHz offset and -118.2 dBc/Hz at a 1 MHz offset from an 18.87 GHz carrier frequency, with a power consumption of 25.65 mW and an area of 0.154 mm2. The peak figure of merit (FoM) is 189.6 dBc/ Hz, and the maximum 1/f3 noise corner frequency is 347 kHz across the FTR.

AB - This paper presents an 18.87-24.19 GHz dual-core, dual-mode voltage-controlled oscillator (VCO) using a multi-tap (MT) inductor-based 2-port resonator with capacitive coupling via a mode-switching block. The 2 -port resonator introduces a gate-to-drain phase shift, suppressing flicker phase noise (PN), while the high-quality factor of the tank minimizes thermal PN. The mode-switching block enables dual resonance modes - high-frequency band (HB) and low-frequency band (LB), achieving a wide frequency tuning range (FTR) and low PN in both the 1/f2 and 1/f3 regions. The proposed VCO is implemented in 65 nm CMOS, and post-layout results show a PN of -68.7 dBc/Hz at a 10 kHz offset and -118.2 dBc/Hz at a 1 MHz offset from an 18.87 GHz carrier frequency, with a power consumption of 25.65 mW and an area of 0.154 mm2. The peak figure of merit (FoM) is 189.6 dBc/ Hz, and the maximum 1/f3 noise corner frequency is 347 kHz across the FTR.

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M3 - Conference contribution

AN - SCOPUS:105029713802

T3 - Midwest Symposium on Circuits and Systems

SP - 941

EP - 945

BT - 2025 IEEE 68th International Midwest Symposium on Circuits and Systems, MWSCAS 2025

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 68th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2025

Y2 - 10 August 2025 through 13 August 2025

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