TY - GEN
T1 - A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology
AU - Hamzaoglu, Fatih
AU - Arslan, Umut
AU - Bisnik, Nabhendra
AU - Ghosh, Swaroop
AU - Lal, Manoj B.
AU - Lindert, Nick
AU - Meterelliyoz, Mesut
AU - Osborne, Randy B.
AU - Park, Joodong
AU - Tomishima, Shigeki
AU - Wang, Yih
AU - Zhang, Kevin
PY - 2014
Y1 - 2014
N2 - CMOS technology scaling continues to drive higher levels of integration in VLSI design, which adds more compute engines on a die. To meet the overall performance-scaling needs, high-speed and high-bandwidth memory is becoming increasingly important. Conventional VLSI systems often rely on on-die SRAMs to address the performance gap between CPU and main memory, DRAM. However, with the rapid growth in capacity needs for high-performance memory, SRAM is not always sufficient to meet the demands of bandwidth-intense applications. Embedded DRAM (eDRAM) has been explored as an alternative to satisfy the high-performance and density needs in memory [1-3]. In this paper, a high-performance eDRAM based on a 22nm tri-gate CMOS technology is introduced. This eDRAM technology enables the integration of an eDRAM cell into the logic technology platform [4]. The design features a well-balanced configuration to achieve both optimal array efficiency and bandwidth. By leveraging the high-performance and low-voltage tri-gate transistor at 22nm generation, the eDRAM achieves a wide range in operating voltage, from 1.1V down to 0.7V, which is essential for low-power logic applications.
AB - CMOS technology scaling continues to drive higher levels of integration in VLSI design, which adds more compute engines on a die. To meet the overall performance-scaling needs, high-speed and high-bandwidth memory is becoming increasingly important. Conventional VLSI systems often rely on on-die SRAMs to address the performance gap between CPU and main memory, DRAM. However, with the rapid growth in capacity needs for high-performance memory, SRAM is not always sufficient to meet the demands of bandwidth-intense applications. Embedded DRAM (eDRAM) has been explored as an alternative to satisfy the high-performance and density needs in memory [1-3]. In this paper, a high-performance eDRAM based on a 22nm tri-gate CMOS technology is introduced. This eDRAM technology enables the integration of an eDRAM cell into the logic technology platform [4]. The design features a well-balanced configuration to achieve both optimal array efficiency and bandwidth. By leveraging the high-performance and low-voltage tri-gate transistor at 22nm generation, the eDRAM achieves a wide range in operating voltage, from 1.1V down to 0.7V, which is essential for low-power logic applications.
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U2 - 10.1109/ISSCC.2014.6757412
DO - 10.1109/ISSCC.2014.6757412
M3 - Conference contribution
AN - SCOPUS:84898063371
SN - 9781479909186
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 230
EP - 231
BT - 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014
Y2 - 9 February 2014 through 13 February 2014
ER -