## Abstract

This article presents a compact 24–30-GHz phased array transceiver (TRX) front end (FE) with high transmitter (TX) power efficiency and low receiver (RX) noise figure (NF) in a 130-nm bipolar CMOS (BiCMOS) technology supporting different 5th generation mobile network (5G) frequency range 2 (FR2) bands (n257, n258, and n261). We introduce an embedded antenna TX/RX (T/R) switch (SW) topology to co-optimize the performances of the power amplifier (PA) and the low-noise amplifier (LNA) while minimizing insertion loss and die area. The proposed TRX integrated circuits (ICs) also integrates a transmission line-based passive phase shifter and 1-bit phase inverter for phase control and a phase-invariant variable gain amplifier (VGA) for gain control, enabling orthogonal phase and gain control in the FE. On-wafer measurements of the TRX FE IC at 25 <inline-formula> <tex-math notation="LaTeX">$^\circ$</tex-math> </inline-formula>C demonstrate TX mode peak power efficiency of 22%–24% and RX-mode NF of 2.8–3.1 dB, including the impact of the antenna T/R switch. The measured <inline-formula> <tex-math notation="LaTeX">$\text{OP1dB}$</tex-math> </inline-formula> and <inline-formula> <tex-math notation="LaTeX">$P_{\rm SAT}$</tex-math> </inline-formula> in the TX mode are 15.6–16.2 and 17.8–18.8 dBm, respectively. RF phase shifting measurements demonstrate <inline-formula> <tex-math notation="LaTeX">$<$</tex-math> </inline-formula>5.6<inline-formula> <tex-math notation="LaTeX">$^\circ$</tex-math> </inline-formula> phase resolution with gain variation lower than <inline-formula> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula>0.5 dB without the need for calibration. We implement phase-invariant gain tunability for orthogonal tapering and beam steering control; the measured phase variation is <inline-formula> <tex-math notation="LaTeX">${<}\pm1.5^\circ$</tex-math> </inline-formula> for 8-dB gain tuning over 24–30 GHz. The IC was measured at a temperature up to 105 <inline-formula> <tex-math notation="LaTeX">$^\circ$</tex-math> </inline-formula>C and maintains TX peak power efficiency <inline-formula> <tex-math notation="LaTeX">$>$</tex-math> </inline-formula> 19% with <inline-formula> <tex-math notation="LaTeX">$P_{\rm SAT}$</tex-math> </inline-formula> degradation <inline-formula> <tex-math notation="LaTeX">$<$</tex-math> </inline-formula> 1 dB and RX NF <inline-formula> <tex-math notation="LaTeX">$<$</tex-math> </inline-formula> 5.1 dB. The IC has an active area of 2.1 <inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.6 mm.

Original language | English (US) |
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Pages (from-to) | 1-17 |

Number of pages | 17 |

Journal | IEEE Journal of Solid-State Circuits |

DOIs | |

State | Accepted/In press - 2024 |

## All Science Journal Classification (ASJC) codes

- Electrical and Electronic Engineering