A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

Saurabh Dighe; Sumeet Kumar Gupta; Vivek De; Sriram Vangal; Nitin Borkar; Shekhar Borkar; Kaushik Roy

A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

Saurabh Dighe
, Sumeet Kumar Gupta
, Vivek De
, Sriram Vangal
, Nitin Borkar
, Shekhar Borkar
, Kaushik Roy

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Scopus citations

Abstract

This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured within-die core-to-core maximum operational frequency (Fmax), leakage & thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21% & chip energy by up to 14.5% across varying voltage/frequency (V/F) operating points & core counts.

Original language	English (US)
Title of host publication	2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
Pages	250-251
Number of pages	2
State	Published - Sep 16 2011
Event	2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan Duration: Jun 15 2011 → Jun 17 2011

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2011 Symposium on VLSI Circuits, VLSIC 2011
Country/Territory	Japan
City	Kyoto
Period	6/15/11 → 6/17/11

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

@inproceedings{73c98f63262648b8a7d204a0ab23ebe2,

title = "A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping",

abstract = "This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes \& presents measured within-die core-to-core maximum operational frequency (Fmax), leakage \& thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS \& optimal core mapping schemes (VA-L \& VA-LV) improve core computation energy by up to 21\% \& chip energy by up to 14.5\% across varying voltage/frequency (V/F) operating points \& core counts.",

author = "Saurabh Dighe and Gupta, \{Sumeet Kumar\} and Vivek De and Sriram Vangal and Nitin Borkar and Shekhar Borkar and Kaushik Roy",

year = "2011",

month = sep,

day = "16",

language = "English (US)",

isbn = "9784863481657",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "250--251",

booktitle = "2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers",

note = "2011 Symposium on VLSI Circuits, VLSIC 2011 ; Conference date: 15-06-2011 Through 17-06-2011",

}

Dighe, S, Gupta, SK, De, V, Vangal, S, Borkar, N, Borkar, S & Roy, K 2011, A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping. in 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers., 5986132, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 250-251, 2011 Symposium on VLSI Circuits, VLSIC 2011, Kyoto, Japan, 6/15/11.

A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping. / Dighe, Saurabh; Gupta, Sumeet Kumar; De, Vivek et al.
2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers. 2011. p. 250-251 5986132 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

AU - Dighe, Saurabh

AU - Gupta, Sumeet Kumar

AU - De, Vivek

AU - Vangal, Sriram

AU - Borkar, Nitin

AU - Borkar, Shekhar

AU - Roy, Kaushik

PY - 2011/9/16

Y1 - 2011/9/16

N2 - This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured within-die core-to-core maximum operational frequency (Fmax), leakage & thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21% & chip energy by up to 14.5% across varying voltage/frequency (V/F) operating points & core counts.

AB - This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured within-die core-to-core maximum operational frequency (Fmax), leakage & thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21% & chip energy by up to 14.5% across varying voltage/frequency (V/F) operating points & core counts.

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M3 - Conference contribution

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BT - 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers

T2 - 2011 Symposium on VLSI Circuits, VLSIC 2011

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ER -

A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

Abstract

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Other

UN SDGs

All Science Journal Classification (ASJC) codes

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