A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation

Saad Bin Nasir; Anto K. Davis; Mohamed Bellaredj; Madhavan Swaminathan; Arijit Raychowdhury; Adam Beece; Don Disney; Yong Wang; Hesam F. Moghadam; Eric Soenen; Jongku Kang; Yasuhiko Mano; Tomoharu Fuji

doi:10.1109/ISCAS.2018.8351653

A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation

Saad Bin Nasir, Anto K. Davis, Mohamed Bellaredj, Madhavan Swaminathan, Arijit Raychowdhury, Adam Beece, Don Disney, Yong Wang, Hesam F. Moghadam, Eric Soenen, Jongku Kang, Yasuhiko Mano, Tomoharu Fuji

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

Digital LDOs enable on-chip fine-grain power management in multi-core microprocessor and system-on-a-chip platforms to increase system level energy efficiency. Their design synthesizability with automatic placement and routing can enable per-core DVFS with quick design turnaround. To enable per-core voltage regulation, this paper showcases a digital LDO designed in 65nm CMOS process. The LDO exhibits core-level high load current driving capability of up to 125mA and a large voltage regulation range of 0.15V to 1.15V. The design employs asynchronous nonlinear control to achieve fast voltage droop mitigation under large load transient events. Measurements show a peak current efficiency of 99.9% and greater than 99.5% at a light load of only 4mA and 1nF load decoupling capacitance.

Original language	English (US)
Title of host publication	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538648810
DOIs	https://doi.org/10.1109/ISCAS.2018.8351653
State	Published - Apr 26 2018
Event	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy Duration: May 27 2018 → May 30 2018

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2018-May
ISSN (Print)	0271-4310

Other

Other	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Country/Territory	Italy
City	Florence
Period	5/27/18 → 5/30/18

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISCAS.2018.8351653

Cite this

Nasir, S. B., Davis, A. K., Bellaredj, M., Swaminathan, M., Raychowdhury, A., Beece, A., Disney, D., Wang, Y., Moghadam, H. F., Soenen, E., Kang, J., Mano, Y., & Fuji, T. (2018). A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings Article 8351653 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2018.8351653

Nasir, Saad Bin ; Davis, Anto K. ; Bellaredj, Mohamed et al. / A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation. 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. (Proceedings - IEEE International Symposium on Circuits and Systems).

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title = "A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation",

abstract = "Digital LDOs enable on-chip fine-grain power management in multi-core microprocessor and system-on-a-chip platforms to increase system level energy efficiency. Their design synthesizability with automatic placement and routing can enable per-core DVFS with quick design turnaround. To enable per-core voltage regulation, this paper showcases a digital LDO designed in 65nm CMOS process. The LDO exhibits core-level high load current driving capability of up to 125mA and a large voltage regulation range of 0.15V to 1.15V. The design employs asynchronous nonlinear control to achieve fast voltage droop mitigation under large load transient events. Measurements show a peak current efficiency of 99.9% and greater than 99.5% at a light load of only 4mA and 1nF load decoupling capacitance.",

author = "Nasir, {Saad Bin} and Davis, {Anto K.} and Mohamed Bellaredj and Madhavan Swaminathan and Arijit Raychowdhury and Adam Beece and Don Disney and Yong Wang and Moghadam, {Hesam F.} and Eric Soenen and Jongku Kang and Yasuhiko Mano and Tomoharu Fuji",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

year = "2018",

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day = "26",

doi = "10.1109/ISCAS.2018.8351653",

language = "English (US)",

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Nasir, SB, Davis, AK, Bellaredj, M, Swaminathan, M, Raychowdhury, A, Beece, A, Disney, D, Wang, Y, Moghadam, HF, Soenen, E, Kang, J, Mano, Y & Fuji, T 2018, A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8351653, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2018-May, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 5/27/18. https://doi.org/10.1109/ISCAS.2018.8351653

A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation. / Nasir, Saad Bin; Davis, Anto K.; Bellaredj, Mohamed et al.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 8351653 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation

AU - Nasir, Saad Bin

AU - Davis, Anto K.

AU - Bellaredj, Mohamed

AU - Swaminathan, Madhavan

AU - Raychowdhury, Arijit

AU - Beece, Adam

AU - Disney, Don

AU - Wang, Yong

AU - Moghadam, Hesam F.

AU - Soenen, Eric

AU - Kang, Jongku

AU - Mano, Yasuhiko

AU - Fuji, Tomoharu

PY - 2018/4/26

Y1 - 2018/4/26

N2 - Digital LDOs enable on-chip fine-grain power management in multi-core microprocessor and system-on-a-chip platforms to increase system level energy efficiency. Their design synthesizability with automatic placement and routing can enable per-core DVFS with quick design turnaround. To enable per-core voltage regulation, this paper showcases a digital LDO designed in 65nm CMOS process. The LDO exhibits core-level high load current driving capability of up to 125mA and a large voltage regulation range of 0.15V to 1.15V. The design employs asynchronous nonlinear control to achieve fast voltage droop mitigation under large load transient events. Measurements show a peak current efficiency of 99.9% and greater than 99.5% at a light load of only 4mA and 1nF load decoupling capacitance.

AB - Digital LDOs enable on-chip fine-grain power management in multi-core microprocessor and system-on-a-chip platforms to increase system level energy efficiency. Their design synthesizability with automatic placement and routing can enable per-core DVFS with quick design turnaround. To enable per-core voltage regulation, this paper showcases a digital LDO designed in 65nm CMOS process. The LDO exhibits core-level high load current driving capability of up to 125mA and a large voltage regulation range of 0.15V to 1.15V. The design employs asynchronous nonlinear control to achieve fast voltage droop mitigation under large load transient events. Measurements show a peak current efficiency of 99.9% and greater than 99.5% at a light load of only 4mA and 1nF load decoupling capacitance.

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M3 - Conference contribution

AN - SCOPUS:85057121284

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018

Y2 - 27 May 2018 through 30 May 2018

ER -

Nasir SB, Davis AK, Bellaredj M, Swaminathan M, Raychowdhury A, Beece A et al. A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. 8351653. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2018.8351653

A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation

Abstract

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All Science Journal Classification (ASJC) codes

UN SDGs

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