TY - GEN
T1 - A built-in self-testing method for embedded multiport memory arrays
AU - Narayanan, V.
AU - Ghosh, S.
AU - Jone, W. B.
AU - Das, S. R.
N1 - Copyright:
Copyright 2011 Elsevier B.V., All rights reserved.
PY - 2004
Y1 - 2004
N2 - Multiport memories are widely used in multi-processor systems, telecommunication ASICs etc. Research papers which define multi-port memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multi-port memories. In this paper, we discuss some basics about the architecture of two-port memories and fault models for the same. We have then used the serial testing mechanism to propose new algorithms which can prove effective to reduce the hardware cost considerably on a chip with many multi-port memories. Once the serial interfacing for two-port memory testing is understood, it can be extended for p-port memories (p>2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead and tolerable test application time.
AB - Multiport memories are widely used in multi-processor systems, telecommunication ASICs etc. Research papers which define multi-port memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multi-port memories. In this paper, we discuss some basics about the architecture of two-port memories and fault models for the same. We have then used the serial testing mechanism to propose new algorithms which can prove effective to reduce the hardware cost considerably on a chip with many multi-port memories. Once the serial interfacing for two-port memory testing is understood, it can be extended for p-port memories (p>2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead and tolerable test application time.
UR - https://www.scopus.com/pages/publications/4644234022
UR - https://www.scopus.com/inward/citedby.url?scp=4644234022&partnerID=8YFLogxK
U2 - 10.1109/IMTC.2004.1351487
DO - 10.1109/IMTC.2004.1351487
M3 - Conference contribution
AN - SCOPUS:4644234022
SN - 078038248X
T3 - Conference Record - IEEE Instrumentation and Measurement Technology Conference
SP - 2027
EP - 2032
BT - Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04
A2 - Demidenko, S.
A2 - Ottoboni, R.
A2 - Petri, D.
A2 - Piuri, V.
A2 - Weng, D.C.T.
T2 - Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04
Y2 - 18 May 2004 through 20 May 2004
ER -