@inproceedings{6067a2a72ca6472984e27c684c80ca06,
title = "A Cache Coherence Protocol for MIN-Based Multiprocessors with Limited Inclusion",
abstract = "In this paper, we look into a feasible approach to incorporating caches into selected switching ele ments of a multistage interconnection network (MIN)- based multiprocessor. Along with the processor private caches, these switch caches form a two-level cache hi erarchy. Selected switch caches within a particular stage of the MIN are connected by a coherence con trol bus, through which a write-invalidate cache coher ence protocol is maintained. Considering scalability and practicality issues, only limited inclusion between the two cache levels is enforced. A simulation-based performance study is conducted to analyze the impact of the protocol on system performance. Comparison between limited and strict inclusion shows that system performance declines with limited inclusion.",
author = "Yousif, {Mazin S.} and Das, {Chita R.} and Thazhuthaveetil, {Matthew J.}",
note = "Publisher Copyright: {\textcopyright} 1993 IEEE.; 1993 International Conference on Parallel Processing, ICPP 1993 ; Conference date: 16-08-1993 Through 20-08-1993",
year = "1993",
doi = "10.1109/ICPP.1993.13",
language = "English (US)",
series = "Proceedings of the International Conference on Parallel Processing",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "254--257",
booktitle = "Architecture",
address = "United States",
}