TY - GEN
T1 - A Cache Coherence Protocol for MIN-Based Multiprocessors with Limited Inclusion
AU - Yousif, Mazin S.
AU - Das, Chita R.
AU - Thazhuthaveetil, Matthew J.
N1 - Funding Information:
This research was supported in part by the National Science Foundation under grant MIP-9104485
Funding Information:
*This research was supported in part by the National Sci¬ ence Foundation under grant MIP-9104485.
Publisher Copyright:
© 1993 IEEE.
PY - 1993
Y1 - 1993
N2 - In this paper, we look into a feasible approach to incorporating caches into selected switching ele ments of a multistage interconnection network (MIN)- based multiprocessor. Along with the processor private caches, these switch caches form a two-level cache hi erarchy. Selected switch caches within a particular stage of the MIN are connected by a coherence con trol bus, through which a write-invalidate cache coher ence protocol is maintained. Considering scalability and practicality issues, only limited inclusion between the two cache levels is enforced. A simulation-based performance study is conducted to analyze the impact of the protocol on system performance. Comparison between limited and strict inclusion shows that system performance declines with limited inclusion.
AB - In this paper, we look into a feasible approach to incorporating caches into selected switching ele ments of a multistage interconnection network (MIN)- based multiprocessor. Along with the processor private caches, these switch caches form a two-level cache hi erarchy. Selected switch caches within a particular stage of the MIN are connected by a coherence con trol bus, through which a write-invalidate cache coher ence protocol is maintained. Considering scalability and practicality issues, only limited inclusion between the two cache levels is enforced. A simulation-based performance study is conducted to analyze the impact of the protocol on system performance. Comparison between limited and strict inclusion shows that system performance declines with limited inclusion.
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U2 - 10.1109/ICPP.1993.13
DO - 10.1109/ICPP.1993.13
M3 - Conference contribution
AN - SCOPUS:77955597379
T3 - Proceedings of the International Conference on Parallel Processing
SP - 254
EP - 257
BT - Architecture
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1993 International Conference on Parallel Processing, ICPP 1993
Y2 - 16 August 1993 through 20 August 1993
ER -