A clock power model to evaluate impact of architectural and technology optimizations

David E. Duarte, N. Vijaykrishnan, Mary Jane Irwin

Research output: Contribution to journalArticlepeer-review

61 Scopus citations


The clock distribution and generation circuitry forms a critical component of current synchronous distal systems and is known to consume at least a quarter of the power budget of existing microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock generation and distribution circuitry, including both the dynamic and leakage power components. The validation results show that the model is reasonably accurate, with the average deviation being within 10% of SPICE simulations. Access to this model can enable further research at high-level design stages in optimizing the system clock power. To illustrate this, a few architectural modifications are considered and their effect on the clock subsystem and the total system power budget is assessed.

Original languageEnglish (US)
Pages (from-to)844-855
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number6
StatePublished - Dec 2002

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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