TY - GEN
T1 - A Compact Ferroelectric 2T-(n+1)C Cell to Implement AND-OR Logic in Memory
AU - Xiao, Yi
AU - Xu, Yixin
AU - Deng, Shan
AU - Zhao, Zijian
AU - George, Sumitha
AU - Ni, Kai
AU - Narayanan, Vijaykrishnan
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - With the proliferation of data-intensive applications, various logic-in-memory (LIM)/ in-memory computing (IMC) solutions are emerging. These solutions aim to mitigate the von Neumann bottleneck caused by frequent data transfer between computational units and memory arrays. Ferroelectric devices such as ferroelectric random access memory (FeRAM), ferroelectric FET (FeFET) and ferroelectric tunnel junction (FTJ) etc., are promising nonvolatile memory (NVM) candidates for the LIM application due to their lower write power compared to competing NVM technologies. In this work, we propose a compact ferroelectric 2T-(n+1) C LIM cell to implement ANDOR logic based on the concept of quasi-nondestructive readout (QNRO) FeRAM. In comparison with 1T-1C FeRAM and 1T FeFET, our structure has both distinguished write and read characteristics. The n-bit AND-OR logic accomplished by our design has 2mathrm{n}times performance improvement and 5.1times integration density gain against the conventional CMOS logic. Additionally, the area efficiency of our design can be further enhanced by 3D integration. We then verify the correctness of a 3-bit AND-OR logic gate by conducting circuit simulation and device experiments. The simulation results demonstrate a sim 70 ON/OFF ratio with the ON/OFF current window of gt866mathrm{nA}, and for the experimental results the mathrm{ON}/mathrm{OFF} ratio is 3.8 with the current window of gt68mumathrm{A}.
AB - With the proliferation of data-intensive applications, various logic-in-memory (LIM)/ in-memory computing (IMC) solutions are emerging. These solutions aim to mitigate the von Neumann bottleneck caused by frequent data transfer between computational units and memory arrays. Ferroelectric devices such as ferroelectric random access memory (FeRAM), ferroelectric FET (FeFET) and ferroelectric tunnel junction (FTJ) etc., are promising nonvolatile memory (NVM) candidates for the LIM application due to their lower write power compared to competing NVM technologies. In this work, we propose a compact ferroelectric 2T-(n+1) C LIM cell to implement ANDOR logic based on the concept of quasi-nondestructive readout (QNRO) FeRAM. In comparison with 1T-1C FeRAM and 1T FeFET, our structure has both distinguished write and read characteristics. The n-bit AND-OR logic accomplished by our design has 2mathrm{n}times performance improvement and 5.1times integration density gain against the conventional CMOS logic. Additionally, the area efficiency of our design can be further enhanced by 3D integration. We then verify the correctness of a 3-bit AND-OR logic gate by conducting circuit simulation and device experiments. The simulation results demonstrate a sim 70 ON/OFF ratio with the ON/OFF current window of gt866mathrm{nA}, and for the experimental results the mathrm{ON}/mathrm{OFF} ratio is 3.8 with the current window of gt68mumathrm{A}.
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U2 - 10.1109/ISVLSI59464.2023.10238503
DO - 10.1109/ISVLSI59464.2023.10238503
M3 - Conference contribution
AN - SCOPUS:85172074328
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
BT - 2023 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2023 - Proceedings
A2 - Kastensmidt, Fernanda
A2 - Reis, Ricardo
A2 - Todri-Sanial, Aida
A2 - Li, Hai
A2 - Metzler, Carolina
PB - IEEE Computer Society
T2 - 26th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2023
Y2 - 20 June 2023 through 23 June 2023
ER -