TY - JOUR
T1 - A compact passive equalizer design for differential channels in TSV-Based 3-D ICs
AU - Fu, Kai
AU - Zhao, Wen Sheng
AU - Wang, Da Wei
AU - Wang, Gaofeng
AU - Swaminathan, Madhavan
AU - Yin, Wen Yan
N1 - Funding Information:
This work was supported in part by the National Natural Science Foundation of China under Grant 61874038, Grant 61504033, Grant 61411136003, and Grant 61431014, in part by the Talent Project of the Zhejiang Association for Science and Technology under Grant 2017YCGC012, and in part by the Open Research Fund of the State Key Lab of Millimeter Waves, Southeast University, under Grant K201910.
Publisher Copyright:
© 2013 IEEE.
PY - 2018
Y1 - 2018
N2 - In this paper, a compact passive equalizer for differential transmission channel is designed in TSV-based three-dimensional integrated circuits (3-D ICs). The compact size of the equalizer is achieved by a square shunt metal line. Three simplified odd-mode half circuit models are proposed for ground-signal-signal-ground (G-S-S-G) type TSVs, differential on-interposer interconnects, and differential channels, respectively. Those simplified models merely consist of frequency-independent elements and can accurately predict the differential insertion losses up to 20 GHz. Moreover, the electrical parameters of the proposed serial resistance-inductance (RL) type equalizers are derived from the system transfer functions and optimized by virtue of the time-domain inter-symbol interference cancellation technique. Further, the geometrical parameters of the RL equalizers are calculated by using a genetic algorithm based multi-objective optimization method. Finally, the performance of the designed RL equalizer is validated by both frequency- and time-domain simulations for 20 Gb/s high-speed differential signaling.
AB - In this paper, a compact passive equalizer for differential transmission channel is designed in TSV-based three-dimensional integrated circuits (3-D ICs). The compact size of the equalizer is achieved by a square shunt metal line. Three simplified odd-mode half circuit models are proposed for ground-signal-signal-ground (G-S-S-G) type TSVs, differential on-interposer interconnects, and differential channels, respectively. Those simplified models merely consist of frequency-independent elements and can accurately predict the differential insertion losses up to 20 GHz. Moreover, the electrical parameters of the proposed serial resistance-inductance (RL) type equalizers are derived from the system transfer functions and optimized by virtue of the time-domain inter-symbol interference cancellation technique. Further, the geometrical parameters of the RL equalizers are calculated by using a genetic algorithm based multi-objective optimization method. Finally, the performance of the designed RL equalizer is validated by both frequency- and time-domain simulations for 20 Gb/s high-speed differential signaling.
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U2 - 10.1109/ACCESS.2018.2884036
DO - 10.1109/ACCESS.2018.2884036
M3 - Article
AN - SCOPUS:85057782843
SN - 2169-3536
VL - 6
SP - 75278
EP - 75292
JO - IEEE Access
JF - IEEE Access
M1 - 8552391
ER -