A compact passive equalizer design for differential channels in TSV-Based 3-D ICs

In this paper, a compact passive equalizer for differential transmission channel is designed in TSV-based three-dimensional integrated circuits (3-D ICs). The compact size of the equalizer is achieved by a square shunt metal line. Three simplified odd-mode half circuit models are proposed for ground-signal-signal-ground (G-S-S-G) type TSVs, differential on-interposer interconnects, and differential channels, respectively. Those simplified models merely consist of frequency-independent elements and can accurately predict the differential insertion losses up to 20 GHz. Moreover, the electrical parameters of the proposed serial resistance-inductance (RL) type equalizers are derived from the system transfer functions and optimized by virtue of the time-domain inter-symbol interference cancellation technique. Further, the geometrical parameters of the RL equalizers are calculated by using a genetic algorithm based multi-objective optimization method. Finally, the performance of the designed RL equalizer is validated by both frequency- and time-domain simulations for 20 Gb/s high-speed differential signaling.