A complete phase-locked loop power consumption model

David Duarte; Vijaykrishnan Narayanan; Mary Jane Irwin

doi:10.1109/DATE.2002.998464

A complete phase-locked loop power consumption model

David Duarte, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Contribution to journal › Conference article › peer-review

10 Scopus citations

Abstract

A PLL power model that accurately estimates the power consumption during both lock and acquisition states is presented. The model is within 5% of circuit level simulation (SPICE) values. No significant power overhead (+/-5% of the power consumed at the final frequency) is incurred during the acquisition process.

Original language	English (US)
Article number	998464
Pages (from-to)	1108
Number of pages	1
Journal	Proceedings -Design, Automation and Test in Europe, DATE
DOIs	https://doi.org/10.1109/DATE.2002.998464
State	Published - 2002
Event	2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France Duration: Mar 4 2002 → Mar 8 2002

All Science Journal Classification (ASJC) codes

General Engineering

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10.1109/DATE.2002.998464

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title = "A complete phase-locked loop power consumption model",

abstract = "A PLL power model that accurately estimates the power consumption during both lock and acquisition states is presented. The model is within 5% of circuit level simulation (SPICE) values. No significant power overhead (+/-5% of the power consumed at the final frequency) is incurred during the acquisition process.",

author = "David Duarte and Vijaykrishnan Narayanan and Irwin, {Mary Jane}",

year = "2002",

doi = "10.1109/DATE.2002.998464",

language = "English (US)",

pages = "1108",

journal = "Proceedings -Design, Automation and Test in Europe, DATE",

issn = "1530-1591",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 ; Conference date: 04-03-2002 Through 08-03-2002",

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AU - Duarte, David

AU - Narayanan, Vijaykrishnan

AU - Irwin, Mary Jane

PY - 2002

Y1 - 2002

N2 - A PLL power model that accurately estimates the power consumption during both lock and acquisition states is presented. The model is within 5% of circuit level simulation (SPICE) values. No significant power overhead (+/-5% of the power consumed at the final frequency) is incurred during the acquisition process.

AB - A PLL power model that accurately estimates the power consumption during both lock and acquisition states is presented. The model is within 5% of circuit level simulation (SPICE) values. No significant power overhead (+/-5% of the power consumed at the final frequency) is incurred during the acquisition process.

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M3 - Conference article

AN - SCOPUS:33847747730

SN - 1530-1591

SP - 1108

JO - Proceedings -Design, Automation and Test in Europe, DATE

JF - Proceedings -Design, Automation and Test in Europe, DATE

M1 - 998464

T2 - 2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002

Y2 - 4 March 2002 through 8 March 2002

ER -

A complete phase-locked loop power consumption model

Abstract

All Science Journal Classification (ASJC) codes

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