A complete phase-locked loop power consumption model

David Duarte, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Contribution to journalConference articlepeer-review

10 Scopus citations


A PLL power model that accurately estimates the power consumption during both lock and acquisition states is presented. The model is within 5% of circuit level simulation (SPICE) values. No significant power overhead (+/-5% of the power consumed at the final frequency) is incurred during the acquisition process.

Original languageEnglish (US)
Article number998464
Number of pages1
JournalProceedings -Design, Automation and Test in Europe, DATE
StatePublished - Dec 1 2002
Event2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France
Duration: Mar 4 2002Mar 8 2002

All Science Journal Classification (ASJC) codes

  • General Engineering


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