TY - JOUR
T1 - A Critical Review of Lithography Methodologies and Impacts of Topography on 2.5-D/3-D Interposers
AU - Liu, Fuhan
AU - Nimbalkar, Pratik
AU - Aslani-Amoli, Nahid
AU - Kathaperumal, Mohanalingam
AU - Tummala, Rao
AU - Swaminathan, Madhavan
N1 - Funding Information:
This work was supported by the Industry Consortium of 3-D Systems Packaging Research Center.
Publisher Copyright:
© 2011-2012 IEEE.
PY - 2023/3/1
Y1 - 2023/3/1
N2 - This article analyzes the lithography design rules in package foundry and wafer foundry and reviews the major lithography techniques for package redistribution layer (RDL) fabrication for panel level 2.5-D/3-D interposers, fan-out packages, and heterogeneous integration. The techniques surveyed in this article are contact aligners, projection aligners/steppers, laser direct writing (LDW), and laser ablation, capable of resolving routing line and space (L/S) of 0.8-1.5 μm with aspect ratio (AR) ≤ 5 and creating microvia with a diameter of 1.5- 2.0 μm at via pitch ≤ 5 μm. The biggest challenge of advanced packaging is scaling the critical dimensions (CDs) on the package to keep up with the pace of scaling of the bump pitch. In addition, there is a critical need for patterning fine lines-and-spaces with high AR to have low resistance traces. These high AR ultra-fine lines and ultra-fine pitch vias are crucial for meeting the needs of high-bandwidth die-to-die interconnections at high input-output (I/O) densities. All these challenges are mainly driven by lithography. With the development of advanced photoresists (PRs), the resolution factor K1 in projection lithography reduces from 0.66 to 0.39, improving the resolution by 40% without the negative impacts on the depth-of-focus (DOF). This article also discusses the specific lithography challenges associated with the topography of multi-layer RDL as well as their impacts on the fabrication of fine features. The fine pitch microvias can be a solution for scaling the I/O pitch down to 5-10 μm as a bumpless way to connect copper pads of known-good-dies to known-good-substrates in fan-out packages.
AB - This article analyzes the lithography design rules in package foundry and wafer foundry and reviews the major lithography techniques for package redistribution layer (RDL) fabrication for panel level 2.5-D/3-D interposers, fan-out packages, and heterogeneous integration. The techniques surveyed in this article are contact aligners, projection aligners/steppers, laser direct writing (LDW), and laser ablation, capable of resolving routing line and space (L/S) of 0.8-1.5 μm with aspect ratio (AR) ≤ 5 and creating microvia with a diameter of 1.5- 2.0 μm at via pitch ≤ 5 μm. The biggest challenge of advanced packaging is scaling the critical dimensions (CDs) on the package to keep up with the pace of scaling of the bump pitch. In addition, there is a critical need for patterning fine lines-and-spaces with high AR to have low resistance traces. These high AR ultra-fine lines and ultra-fine pitch vias are crucial for meeting the needs of high-bandwidth die-to-die interconnections at high input-output (I/O) densities. All these challenges are mainly driven by lithography. With the development of advanced photoresists (PRs), the resolution factor K1 in projection lithography reduces from 0.66 to 0.39, improving the resolution by 40% without the negative impacts on the depth-of-focus (DOF). This article also discusses the specific lithography challenges associated with the topography of multi-layer RDL as well as their impacts on the fabrication of fine features. The fine pitch microvias can be a solution for scaling the I/O pitch down to 5-10 μm as a bumpless way to connect copper pads of known-good-dies to known-good-substrates in fan-out packages.
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U2 - 10.1109/TCPMT.2023.3265568
DO - 10.1109/TCPMT.2023.3265568
M3 - Article
AN - SCOPUS:85153355347
SN - 2156-3950
VL - 13
SP - 291
EP - 299
JO - IEEE Transactions on Components, Packaging and Manufacturing Technology
JF - IEEE Transactions on Components, Packaging and Manufacturing Technology
IS - 3
ER -