A digitally adjustable resistor for path delay characterization in high-frequency microprocessors

M. Saint-Laurent, M. Swaminathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Scopus citations

Abstract

Most high-frequency microprocessors have a clock distribution network allowing the manipulation of the clock edges to facilitate silicon debug and path delay characterization. Typically, a particular edge of the clock is skewed using a variable-delay element until a failure occurs. This paper describes a digitally adjustable resistor applied to the construction of such a variable-delay element. The operation of the digitally adjustable resistor is explained. A strategy to choose the control bits for the resistor is also discussed. The proposed variable-delay element can achieve a 1-ps resolution over a 50-ps range in a 180-nm fabrication technology.

Original languageEnglish (US)
Title of host publication2001 Southwest Symposium on Mixed-Signal Design, SSMSD 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages61-64
Number of pages4
ISBN (Electronic)0780367421, 9780780367425
DOIs
StatePublished - 2001
EventSouthwest Symposium on Mixed-Signal Design, SSMSD 2001 - Austin, United States
Duration: Feb 25 2001Feb 27 2001

Publication series

Name2001 Southwest Symposium on Mixed-Signal Design, SSMSD 2001

Conference

ConferenceSouthwest Symposium on Mixed-Signal Design, SSMSD 2001
Country/TerritoryUnited States
CityAustin
Period2/25/012/27/01

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Signal Processing
  • Electrical and Electronic Engineering

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