@inproceedings{701e4deba1874982860ec6a35955da0f,
title = "A digitally adjustable resistor for path delay characterization in high-frequency microprocessors",
abstract = "Most high-frequency microprocessors have a clock distribution network allowing the manipulation of the clock edges to facilitate silicon debug and path delay characterization. Typically, a particular edge of the clock is skewed using a variable-delay element until a failure occurs. This paper describes a digitally adjustable resistor applied to the construction of such a variable-delay element. The operation of the digitally adjustable resistor is explained. A strategy to choose the control bits for the resistor is also discussed. The proposed variable-delay element can achieve a 1-ps resolution over a 50-ps range in a 180-nm fabrication technology.",
author = "M. Saint-Laurent and M. Swaminathan",
note = "Publisher Copyright: {\textcopyright} 2001 IEEE.; Southwest Symposium on Mixed-Signal Design, SSMSD 2001 ; Conference date: 25-02-2001 Through 27-02-2001",
year = "2001",
doi = "10.1109/SSMSD.2001.914938",
language = "English (US)",
series = "2001 Southwest Symposium on Mixed-Signal Design, SSMSD 2001",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "61--64",
booktitle = "2001 Southwest Symposium on Mixed-Signal Design, SSMSD 2001",
address = "United States",
}