TY - GEN
T1 - A generic and reconfigurable test paradigm using low-cost integrated poly-Si TFTs
AU - Li, Jing
AU - Ghosh, Swaroop
AU - Roy, Kaushik
PY - 2007/1/1
Y1 - 2007/1/1
N2 - In this work, we propose a novel low power, process tolerant, generic and reconfigurable test structure to reduce the test cost, improve diagnosability and verifiability of complex VLSI systems. The test structure contains a variety of configurable design-for-test units designed with low cost Low Temperature Polycrystalline Silicon Thin Film Transistors (LTPS TFTs) that are fabricated on a separate substrate (e.g., polymer, glass etc). The proposed test circuits do not consume any silicon area because they can be integrated on the chip using 3-D technology. This reconfigurable test paradigm eliminates the need to re-design the BIST components that may vary from one processor generation to another.
AB - In this work, we propose a novel low power, process tolerant, generic and reconfigurable test structure to reduce the test cost, improve diagnosability and verifiability of complex VLSI systems. The test structure contains a variety of configurable design-for-test units designed with low cost Low Temperature Polycrystalline Silicon Thin Film Transistors (LTPS TFTs) that are fabricated on a separate substrate (e.g., polymer, glass etc). The proposed test circuits do not consume any silicon area because they can be integrated on the chip using 3-D technology. This reconfigurable test paradigm eliminates the need to re-design the BIST components that may vary from one processor generation to another.
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U2 - 10.1109/TEST.2007.4437622
DO - 10.1109/TEST.2007.4437622
M3 - Conference contribution
SN - 1424411289
SN - 9781424411283
T3 - Proceedings - International Test Conference
BT - 2007 IEEE International Test Conference, ITC
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2007 IEEE International Test Conference, ITC
Y2 - 23 October 2007 through 25 October 2007
ER -