A generic reconfigurable neural network architecture implemented as a network on chip

T. Theocharides; G. Link; N. Vijaykrishnan; M. J. Irwin; V. Srikantam

A generic reconfigurable neural network architecture implemented as a network on chip

T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin, V. Srikantam

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Neural networks are widely used in pattern recognition, security applications and data manipulation. We propose a novel hardware architecture for a generic neural network, using Network on Chip (NoC) interconnect. The proposed architecture allows for expandability, mapping of more than one logical unit onto a single physical unit, and dynamic reconfiguration based on application-specific demands. Simulation results show that this architecture has significant performance benefits over existing architectures.

Original language	English (US)
Title of host publication	Proceedings - IEEE International SOC Conference
Editors	J. Chickanosky, D. Ha, R. Auletta
Pages	191-194
Number of pages	4
State	Published - Dec 1 2004
Event	Proceedings - IEEE International SOC Conference - Santa Clara, CA, United States Duration: Sep 12 2004 → Sep 15 2004

Publication series

Name	Proceedings - IEEE International SOC Conference

Other

Other	Proceedings - IEEE International SOC Conference
Country/Territory	United States
City	Santa Clara, CA
Period	9/12/04 → 9/15/04

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

@inproceedings{f47a36e1aa1241418ca2341faf0e3504,

title = "A generic reconfigurable neural network architecture implemented as a network on chip",

abstract = "Neural networks are widely used in pattern recognition, security applications and data manipulation. We propose a novel hardware architecture for a generic neural network, using Network on Chip (NoC) interconnect. The proposed architecture allows for expandability, mapping of more than one logical unit onto a single physical unit, and dynamic reconfiguration based on application-specific demands. Simulation results show that this architecture has significant performance benefits over existing architectures.",

author = "T. Theocharides and G. Link and N. Vijaykrishnan and Irwin, {M. J.} and V. Srikantam",

year = "2004",

month = dec,

day = "1",

language = "English (US)",

isbn = "0780384458",

series = "Proceedings - IEEE International SOC Conference",

pages = "191--194",

editor = "J. Chickanosky and D. Ha and R. Auletta",

booktitle = "Proceedings - IEEE International SOC Conference",

note = "Proceedings - IEEE International SOC Conference ; Conference date: 12-09-2004 Through 15-09-2004",

}

Theocharides, T, Link, G, Vijaykrishnan, N, Irwin, MJ & Srikantam, V 2004, A generic reconfigurable neural network architecture implemented as a network on chip. in J Chickanosky, D Ha & R Auletta (eds), Proceedings - IEEE International SOC Conference., TA1.3, Proceedings - IEEE International SOC Conference, pp. 191-194, Proceedings - IEEE International SOC Conference, Santa Clara, CA, United States, 9/12/04.

A generic reconfigurable neural network architecture implemented as a network on chip. / Theocharides, T.; Link, G.; Vijaykrishnan, N. et al.
Proceedings - IEEE International SOC Conference. ed. / J. Chickanosky; D. Ha; R. Auletta. 2004. p. 191-194 TA1.3 (Proceedings - IEEE International SOC Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A generic reconfigurable neural network architecture implemented as a network on chip

AU - Theocharides, T.

AU - Link, G.

AU - Vijaykrishnan, N.

AU - Irwin, M. J.

AU - Srikantam, V.

PY - 2004/12/1

Y1 - 2004/12/1

N2 - Neural networks are widely used in pattern recognition, security applications and data manipulation. We propose a novel hardware architecture for a generic neural network, using Network on Chip (NoC) interconnect. The proposed architecture allows for expandability, mapping of more than one logical unit onto a single physical unit, and dynamic reconfiguration based on application-specific demands. Simulation results show that this architecture has significant performance benefits over existing architectures.

AB - Neural networks are widely used in pattern recognition, security applications and data manipulation. We propose a novel hardware architecture for a generic neural network, using Network on Chip (NoC) interconnect. The proposed architecture allows for expandability, mapping of more than one logical unit onto a single physical unit, and dynamic reconfiguration based on application-specific demands. Simulation results show that this architecture has significant performance benefits over existing architectures.

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M3 - Conference contribution

AN - SCOPUS:14844337467

SN - 0780384458

SN - 9780780384453

T3 - Proceedings - IEEE International SOC Conference

SP - 191

EP - 194

BT - Proceedings - IEEE International SOC Conference

A2 - Chickanosky, J.

A2 - Ha, D.

A2 - Auletta, R.

T2 - Proceedings - IEEE International SOC Conference

Y2 - 12 September 2004 through 15 September 2004

ER -

A generic reconfigurable neural network architecture implemented as a network on chip

Abstract

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