A hardware design language for timing-sensitive information-flow security

Keyphrases

• Caching 100%
• Information Security 100%
• Information Flow 66%
• Timing Channels 66%
• Hardware Design 33%
• Low Overhead 33%
• Non-interference 33%
• Information Channel 33%
• Verilog 33%
• MIPS Processor 33%
• Probing Attacks 33%
• Secure Information Flow 33%
• Hardware Features 33%
• Hardware Level 33%
• Type Annotations 33%

Computer Science

• Sensitive Informations 100%
• Hardware Design 100%
• Design Language 100%
• Hardware Level 66%
• Annotation 33%
• Information Security 33%
• Verilog 33%
• Information Channel 33%