TY - GEN
T1 - A hardware-software codesign strategy for loop intensive applications
AU - Zhang, Yuanrui
AU - Kandemir, Mahmut
PY - 2009
Y1 - 2009
N2 - Hardware-software codesign is a powerful technique that can be used to build complex systems. In this paper, we propose a compiler driven hardware-software codesign strategy that works at application level, aiming at facilitating algorithm architecture co-explorations. The proposed approach employs an intermediate code representation, called Loop Hierarchy Tree (LHT), to perform codesign exploration, and applies a branchand- bound search to find a hardware-software partitioning that minimizes execution latency under the given area constraints. We also developed fast cost estimation models for LHT and can be extended to handle codesign for more complex hybrid architectures. Experimental results show that our approach is successful in finding good solutions for the applications on thetarget codesign platform.
AB - Hardware-software codesign is a powerful technique that can be used to build complex systems. In this paper, we propose a compiler driven hardware-software codesign strategy that works at application level, aiming at facilitating algorithm architecture co-explorations. The proposed approach employs an intermediate code representation, called Loop Hierarchy Tree (LHT), to perform codesign exploration, and applies a branchand- bound search to find a hardware-software partitioning that minimizes execution latency under the given area constraints. We also developed fast cost estimation models for LHT and can be extended to handle codesign for more complex hybrid architectures. Experimental results show that our approach is successful in finding good solutions for the applications on thetarget codesign platform.
UR - http://www.scopus.com/inward/record.url?scp=70350769241&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70350769241&partnerID=8YFLogxK
U2 - 10.1109/SASP.2009.5226327
DO - 10.1109/SASP.2009.5226327
M3 - Conference contribution
AN - SCOPUS:70350769241
SN - 9781424449385
T3 - 2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009
SP - 107
EP - 113
BT - 2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009
T2 - 2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009
Y2 - 27 July 2009 through 28 July 2009
ER -