A heuristic for clock selection in high-level synthesis

J. Ramanujam; S. Deshpande; J. Hong; M. Kandemir

doi:10.1109/ASPDAC.2002.994956

A heuristic for clock selection in high-level synthesis

J. Ramanujam, S. Deshpande, J. Hong, M. Kandemir

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Scopus citations

Abstract

Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.

Original language	English (US)
Title of host publication	Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	414-419
Number of pages	6
ISBN (Electronic)	0769514413, 9780769514413
DOIs	https://doi.org/10.1109/ASPDAC.2002.994956
State	Published - 2002
Event	7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 - Bangalore, India Duration: Jan 7 2002 → Jan 11 2002

Publication series

Name	Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Other

Other	7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Country/Territory	India
City	Bangalore
Period	1/7/02 → 1/11/02

All Science Journal Classification (ASJC) codes

Computer Graphics and Computer-Aided Design
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2002.994956

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Ramanujam, J., Deshpande, S., Hong, J., & Kandemir, M. (2002). A heuristic for clock selection in high-level synthesis. In Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 (pp. 414-419). Article 994956 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2002.994956

Ramanujam, J. ; Deshpande, S. ; Hong, J. et al. / A heuristic for clock selection in high-level synthesis. Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 414-419 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).

@inproceedings{95f5db7a28754727bf771f840987a753,

title = "A heuristic for clock selection in high-level synthesis",

abstract = "Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.",

author = "J. Ramanujam and S. Deshpande and J. Hong and M. Kandemir",

note = "Funding Information: Acknowledgments J. Ramanujam has been supported in part by NSF Young Investigator Award 9457768 and NSF grants 0073800 and 0121706. Mahmut Kandemir is supported in part by NSF CAREER award 0093082. Publisher Copyright: {\textcopyright} 2002 IEEE.; 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 ; Conference date: 07-01-2002 Through 11-01-2002",

year = "2002",

doi = "10.1109/ASPDAC.2002.994956",

language = "English (US)",

series = "Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "414--419",

booktitle = "Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002",

address = "United States",

}

Ramanujam, J, Deshpande, S, Hong, J & Kandemir, M 2002, A heuristic for clock selection in high-level synthesis. in Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002., 994956, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, Institute of Electrical and Electronics Engineers Inc., pp. 414-419, 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, Bangalore, India, 1/7/02. https://doi.org/10.1109/ASPDAC.2002.994956

A heuristic for clock selection in high-level synthesis. / Ramanujam, J.; Deshpande, S.; Hong, J. et al.
Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 414-419 994956 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A heuristic for clock selection in high-level synthesis

AU - Ramanujam, J.

AU - Deshpande, S.

AU - Hong, J.

AU - Kandemir, M.

N1 - Funding Information: Acknowledgments J. Ramanujam has been supported in part by NSF Young Investigator Award 9457768 and NSF grants 0073800 and 0121706. Mahmut Kandemir is supported in part by NSF CAREER award 0093082. Publisher Copyright: © 2002 IEEE.

PY - 2002

Y1 - 2002

N2 - Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.

AB - Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.

UR - http://www.scopus.com/inward/record.url?scp=84962311513&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84962311513&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2002.994956

DO - 10.1109/ASPDAC.2002.994956

M3 - Conference contribution

AN - SCOPUS:84962311513

T3 - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

SP - 414

EP - 419

BT - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Y2 - 7 January 2002 through 11 January 2002

ER -

Ramanujam J, Deshpande S, Hong J, Kandemir M. A heuristic for clock selection in high-level synthesis. In Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 414-419. 994956. (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). doi: 10.1109/ASPDAC.2002.994956

A heuristic for clock selection in high-level synthesis

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