A heuristic for clock selection in high-level synthesis

J. Ramanujam; S. Deshpande; J. Hong; M. Kandemir

doi:10.1109/ASPDAC.2002.994956

A heuristic for clock selection in high-level synthesis

J. Ramanujam, S. Deshpande, J. Hong, M. Kandemir

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Scopus citations

Abstract

Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.

Original language	English (US)
Title of host publication	Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	414-419
Number of pages	6
ISBN (Electronic)	0769514413, 9780769514413
DOIs	https://doi.org/10.1109/ASPDAC.2002.994956
State	Published - 2002
Event	7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 - Bangalore, India Duration: Jan 7 2002 → Jan 11 2002

Publication series

Name	Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Other

Other	7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Country/Territory	India
City	Bangalore
Period	1/7/02 → 1/11/02

All Science Journal Classification (ASJC) codes

Computer Graphics and Computer-Aided Design
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2002.994956

Cite this

Ramanujam, J., Deshpande, S., Hong, J., & Kandemir, M. (2002). A heuristic for clock selection in high-level synthesis. In Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 (pp. 414-419). Article 994956 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2002.994956

Ramanujam, J. ; Deshpande, S. ; Hong, J. et al. / A heuristic for clock selection in high-level synthesis. Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 414-419 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).

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abstract = "Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.",

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year = "2002",

doi = "10.1109/ASPDAC.2002.994956",

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Ramanujam, J, Deshpande, S, Hong, J & Kandemir, M 2002, A heuristic for clock selection in high-level synthesis. in Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002., 994956, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, Institute of Electrical and Electronics Engineers Inc., pp. 414-419, 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, Bangalore, India, 1/7/02. https://doi.org/10.1109/ASPDAC.2002.994956

A heuristic for clock selection in high-level synthesis. / Ramanujam, J.; Deshpande, S.; Hong, J. et al.
Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 414-419 994956 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.

AB - Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.

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Ramanujam J, Deshpande S, Hong J, Kandemir M. A heuristic for clock selection in high-level synthesis. In Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 414-419. 994956. (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). doi: 10.1109/ASPDAC.2002.994956

A heuristic for clock selection in high-level synthesis

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