@inproceedings{2edf41f408914cffbd898914ebc77546,
title = "A high-speed power and resolution adaptive flash analog-to-digital converter",
abstract = "A high-speed and small-area power and resolution adaptive flash ADC is presented. The High-Speed Power and Resolution Adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.",
author = "Sunny Nahata and Kyusun Choi and Jincheol Yoo",
year = "2004",
language = "English (US)",
isbn = "0780384458",
series = "Proceedings - IEEE International SOC Conference",
pages = "33--36",
editor = "J. Chickanosky and D. Ha and R. Auletta",
booktitle = "Proceedings - IEEE International SOC Conference",
note = "Proceedings - IEEE International SOC Conference ; Conference date: 12-09-2004 Through 15-09-2004",
}