A hybrid NoC design for cache coherence optimization for chip multiprocessors

Hui Zhao, Ohyoung Jang, Wei Ding, Yuanrui Zhang, Mahmut Kandemir, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations


On chip many-core systems, evolving from prior multi-processor systems, are considered as a promising solution to the performance scalability and power consumption problems. The long communication distance between the traditional multi-processors makes directory-based cache coherence protocols better solutions compared to bus-based snooping protocols even with the overheads from indirections. However, much smaller distances between the CMP cores enhance the reachability of buses, revitalizing the applicability of snooping protocols for cache-to-cache transfers. In this work, we propose a hybrid NoC design to provide optimized support for cache coherency. In our design, on-chip links can be dynamically configured as either point-to-point links between NoC nodes or short buses to facilitate localized snooping. By taking advantage of the best of both worlds, bus-based snooping coherency and NoC-based directory coherency, our approach brings both power and performance benefits.

Original languageEnglish (US)
Title of host publicationProceedings of the 49th Annual Design Automation Conference, DAC '12
Number of pages9
StatePublished - 2012
Event49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States
Duration: Jun 3 2012Jun 7 2012

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other49th Annual Design Automation Conference, DAC '12
Country/TerritoryUnited States
CitySan Francisco, CA

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation


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