TY - GEN
T1 - A multi-PLL clock distribution architecture for gigascale integration
AU - Saint-Laurent, M.
AU - Swaminathan, M.
N1 - Publisher Copyright:
© 2001 IEEE.
PY - 2001
Y1 - 2001
N2 - This paper proposes a new semi-distributed architecture for clock distribution that is suitable for gigascale integration. First, the limitations associated with conventional clock distribution networks are discussed. Next, some of the alternative solutions to the clock distribution problem are reviewed and compared in terms of architecture, power dissipation, clock inaccuracy, and ease of implementation. The compatibility of the alternatives with established design-for-testability and design-for-debuggability techniques is also evaluated. Then, the proposed architecture is introduced. It employs an array of phase-locked loops (PLLs) synchronized using digital feedback. The new architecture addresses the limitations associated with conventional clocking networks, but does not suffer from the practical shortcomings affecting the alternatives proposed so far.
AB - This paper proposes a new semi-distributed architecture for clock distribution that is suitable for gigascale integration. First, the limitations associated with conventional clock distribution networks are discussed. Next, some of the alternative solutions to the clock distribution problem are reviewed and compared in terms of architecture, power dissipation, clock inaccuracy, and ease of implementation. The compatibility of the alternatives with established design-for-testability and design-for-debuggability techniques is also evaluated. Then, the proposed architecture is introduced. It employs an array of phase-locked loops (PLLs) synchronized using digital feedback. The new architecture addresses the limitations associated with conventional clocking networks, but does not suffer from the practical shortcomings affecting the alternatives proposed so far.
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U2 - 10.1109/IWV.2001.923136
DO - 10.1109/IWV.2001.923136
M3 - Conference contribution
AN - SCOPUS:84964545107
T3 - Proceedings - IEEE Computer Society Workshop on VLSI, WVLSI 2001
SP - 30
EP - 35
BT - Proceedings - IEEE Computer Society Workshop on VLSI, WVLSI 2001
A2 - Smailagic, Asim
A2 - De Man, Hugo
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE Computer Society Workshop on VLSI 2001, WVLSI 2001
Y2 - 19 April 2001 through 20 April 2001
ER -