A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-κ gate-dielectric MOSFETs

M. Jagadesh Kumar; Vivek Venkataraman; Sumeet Kumar Gupta

doi:10.1109/TED.2006.882268

A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-κ gate-dielectric MOSFETs

M. Jagadesh Kumar, Vivek Venkataraman, Sumeet Kumar Gupta

Electrical Engineering

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

A grounded lamination gate (GLG) structure for high-κ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.

Original language	English (US)
Pages (from-to)	2578-2581
Number of pages	4
Journal	IEEE Transactions on Electron Devices
Volume	53
Issue number	10
DOIs	https://doi.org/10.1109/TED.2006.882268
State	Published - 2006

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2006.882268

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abstract = "A grounded lamination gate (GLG) structure for high-κ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.",

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AU - Gupta, Sumeet Kumar

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AB - A grounded lamination gate (GLG) structure for high-κ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.

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A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-κ gate-dielectric MOSFETs

Abstract

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