@inproceedings{05e95eaf6fec4f4180945fbbcfc49379,
title = "A New Grounded Lamination Gate (GLG) SOI MOSFET for diminished fringe capacitance effects",
abstract = "A new Grounded Lamination Gate (GLG) structure is proposed in which grounded metal film is deposited in the spacer region on both sides of the gate to prevent the fringing field lines emanating from the bottom of the gate electrode from entering the source/drain regions. The variation of threshold voltage with gate dielectric permittivity is obtained for both the GLG and the conventional SOI MOSFETs using MEDICI. We demonstrate that the application of grounded lamination gate (GLG) structure is very effective in controlling the threshold voltage roll-off even for high gate dielectric permittivities.",
author = "{Jagadesh Kumar}, M. and Vivek Venkataraman and Gupta, {Sumeet Kumar}",
year = "2006",
month = dec,
day = "8",
language = "English (US)",
isbn = "0976798565",
series = "2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings",
pages = "709--712",
booktitle = "2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings",
note = "2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings ; Conference date: 07-05-2006 Through 11-05-2006",
}