A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM: IBM/Macronix Phase Change Memory Joint Project

N. Gong, W. Chien, Y. Chou, C. Yeh, N. Li, H. Cheng, C. Cheng, I. Kuo, C. Yang, R. Bruce, A. Ray, L. Gignac, Y. Lin, C. Miller, T. Perri, W. Kim, L. Buzi, H. Utomo, F. Carta, E. LaiH. Ho, H. Lung, M. Brightsky

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations


We present the first MLC operation for OTS-PCM with comprehensive operation algorithm study. An ADM chip with fast write speed (<300ns) and robust operation (> 109 cycles) are shown indicating the potential for high performance MLC OTS-PCM. A desirable 2-bits/cell operation up to 108 cycles without further read verification is achieved based on 100 cells data from 1Mbit crosspoint array. Systematic discussions of MLC operation under '1/2V' scheme is further presented, and threshold voltage (Vt) drift is evaluated accordingly.

Original languageEnglish (US)
Title of host publication2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728164601
StatePublished - Jun 2020
Event2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Honolulu, United States
Duration: Jun 16 2020Jun 19 2020

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562


Conference2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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