A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM: IBM/Macronix Phase Change Memory Joint Project

N. Gong; W. Chien; Y. Chou; C. Yeh; N. Li; H. Cheng; C. Cheng; I. Kuo; C. Yang; R. Bruce; A. Ray; L. Gignac; Y. Lin; C. Miller; T. Perri; W. Kim; L. Buzi; H. Utomo; F. Carta; E. Lai; H. Ho; H. Lung; M. Brightsky

doi:10.1109/VLSITechnology18217.2020.9265020

A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM: IBM/Macronix Phase Change Memory Joint Project

N. Gong
, W. Chien
, Y. Chou
, C. Yeh
, N. Li
, H. Cheng
, C. Cheng
, I. Kuo
, C. Yang
, R. Bruce
, A. Ray
, L. Gignac
, Y. Lin
, C. Miller
, T. Perri
, W. Kim
, L. Buzi
, H. Utomo
, F. Carta
, E. Lai

H. Ho, H. Lung, M. Brightsky

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Scopus citations

Abstract

We present the first MLC operation for OTS-PCM with comprehensive operation algorithm study. An ADM chip with fast write speed (<300ns) and robust operation (> 109 cycles) are shown indicating the potential for high performance MLC OTS-PCM. A desirable 2-bits/cell operation up to 108 cycles without further read verification is achieved based on 100 cells data from 1Mbit crosspoint array. Systematic discussions of MLC operation under '1/2V' scheme is further presented, and threshold voltage (Vt) drift is evaluated accordingly.

Original language	English (US)
Title of host publication	2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728164601
DOIs	https://doi.org/10.1109/VLSITechnology18217.2020.9265020
State	Published - Jun 2020
Event	2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Honolulu, United States Duration: Jun 16 2020 → Jun 19 2020

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2020-June
ISSN (Print)	0743-1562

Conference

Conference	2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020
Country/Territory	United States
City	Honolulu
Period	6/16/20 → 6/19/20

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/VLSITechnology18217.2020.9265020

Cite this

Gong, N., Chien, W., Chou, Y., Yeh, C., Li, N., Cheng, H., Cheng, C., Kuo, I., Yang, C., Bruce, R., Ray, A., Gignac, L., Lin, Y., Miller, C., Perri, T., Kim, W., Buzi, L., Utomo, H., Carta, F., ... Brightsky, M. (2020). A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM: IBM/Macronix Phase Change Memory Joint Project. In 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings Article 9265020 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2020-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnology18217.2020.9265020

@inproceedings{d0b35d3402ef44239e474f50b35286ee,

title = "A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM: IBM/Macronix Phase Change Memory Joint Project",

abstract = "We present the first MLC operation for OTS-PCM with comprehensive operation algorithm study. An ADM chip with fast write speed (<300ns) and robust operation (> 109 cycles) are shown indicating the potential for high performance MLC OTS-PCM. A desirable 2-bits/cell operation up to 108 cycles without further read verification is achieved based on 100 cells data from 1Mbit crosspoint array. Systematic discussions of MLC operation under '1/2V' scheme is further presented, and threshold voltage (Vt) drift is evaluated accordingly.",

author = "N. Gong and W. Chien and Y. Chou and C. Yeh and N. Li and H. Cheng and C. Cheng and I. Kuo and C. Yang and R. Bruce and A. Ray and L. Gignac and Y. Lin and C. Miller and T. Perri and W. Kim and L. Buzi and H. Utomo and F. Carta and E. Lai and H. Ho and H. Lung and M. Brightsky",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 ; Conference date: 16-06-2020 Through 19-06-2020",

year = "2020",

month = jun,

doi = "10.1109/VLSITechnology18217.2020.9265020",

language = "English (US)",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings",

address = "United States",

}

Gong, N, Chien, W, Chou, Y, Yeh, C, Li, N, Cheng, H, Cheng, C, Kuo, I, Yang, C, Bruce, R, Ray, A, Gignac, L, Lin, Y, Miller, C, Perri, T, Kim, W, Buzi, L, Utomo, H, Carta, F, Lai, E, Ho, H, Lung, H & Brightsky, M 2020, A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM: IBM/Macronix Phase Change Memory Joint Project. in 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings., 9265020, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2020-June, Institute of Electrical and Electronics Engineers Inc., 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020, Honolulu, United States, 6/16/20. https://doi.org/10.1109/VLSITechnology18217.2020.9265020

A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM: IBM/Macronix Phase Change Memory Joint Project. / Gong, N.; Chien, W.; Chou, Y. et al.
2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9265020 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2020-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM

T2 - 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020

AU - Gong, N.

AU - Chien, W.

AU - Chou, Y.

AU - Yeh, C.

AU - Li, N.

AU - Cheng, H.

AU - Cheng, C.

AU - Kuo, I.

AU - Yang, C.

AU - Bruce, R.

AU - Ray, A.

AU - Gignac, L.

AU - Lin, Y.

AU - Miller, C.

AU - Perri, T.

AU - Kim, W.

AU - Buzi, L.

AU - Utomo, H.

AU - Carta, F.

AU - Lai, E.

AU - Ho, H.

AU - Lung, H.

AU - Brightsky, M.

PY - 2020/6

Y1 - 2020/6

N2 - We present the first MLC operation for OTS-PCM with comprehensive operation algorithm study. An ADM chip with fast write speed (<300ns) and robust operation (> 109 cycles) are shown indicating the potential for high performance MLC OTS-PCM. A desirable 2-bits/cell operation up to 108 cycles without further read verification is achieved based on 100 cells data from 1Mbit crosspoint array. Systematic discussions of MLC operation under '1/2V' scheme is further presented, and threshold voltage (Vt) drift is evaluated accordingly.

AB - We present the first MLC operation for OTS-PCM with comprehensive operation algorithm study. An ADM chip with fast write speed (<300ns) and robust operation (> 109 cycles) are shown indicating the potential for high performance MLC OTS-PCM. A desirable 2-bits/cell operation up to 108 cycles without further read verification is achieved based on 100 cells data from 1Mbit crosspoint array. Systematic discussions of MLC operation under '1/2V' scheme is further presented, and threshold voltage (Vt) drift is evaluated accordingly.

UR - https://www.scopus.com/pages/publications/85098202331

UR - https://www.scopus.com/pages/publications/85098202331#tab=citedBy

U2 - 10.1109/VLSITechnology18217.2020.9265020

DO - 10.1109/VLSITechnology18217.2020.9265020

M3 - Conference contribution

AN - SCOPUS:85098202331

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 16 June 2020 through 19 June 2020

ER -

Gong N, Chien W, Chou Y, Yeh C, Li N, Cheng H et al. A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM: IBM/Macronix Phase Change Memory Joint Project. In 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9265020. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnology18217.2020.9265020

A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM: IBM/Macronix Phase Change Memory Joint Project

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