A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs

E. Syam Sundar; Vikram Chandrasekhar; M. Sashikanth; V. Kamakoti; Vijaykrishnan Narayanan

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs

E. Syam Sundar, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a new CLB architecture for FPGAs that can detect and correct Single Event Upset (SEU) faults in the LUTs. A methodology for mapping logical functions onto the LUTs is presented that exploits the features of the proposed CLB architecture to detect and correct the SEU faults in the LUTs. Experimental results obtained by mapping standard benchmark circuits on the proposed architecture indicate that on an average, 96% of the SEU in the LUTs can be detected without employing any redundancy. Further, by using Duplication with Comparison (DWC) techniques it is shown that 100% of the SEU in the LUTs can be detected for any circuit that is mapped on the proposed architecture; and for the benchmark circuits, on an average, 96% of the SEU in the LUTs can be automatically (without any user intervention or reconfiguration) corrected.

Original language	English (US)
Title of host publication	Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04
Editors	O. Diessel, J. Williams
Pages	121-128
Number of pages	8
State	Published - Dec 1 2004
Event	2004 IEEE International Conference on Field-Programmable Technology, FPT '04 - Brisbane, Australia Duration: Dec 6 2004 → Dec 8 2004

Publication series

Name	Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

Other

Other	2004 IEEE International Conference on Field-Programmable Technology, FPT '04
Country/Territory	Australia
City	Brisbane
Period	12/6/04 → 12/8/04

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

Sundar, E. S., Chandrasekhar, V., Sashikanth, M., Kamakoti, V., & Narayanan, V. (2004). A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. In O. Diessel, & J. Williams (Eds.), Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04 (pp. 121-128). (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

Sundar, E. Syam ; Chandrasekhar, Vikram ; Sashikanth, M. et al. / A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. editor / O. Diessel ; J. Williams. 2004. pp. 121-128 (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

@inproceedings{aae33cb24b934fa6bc4c1a75d5aca819,

title = "A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs",

abstract = "This paper proposes a new CLB architecture for FPGAs that can detect and correct Single Event Upset (SEU) faults in the LUTs. A methodology for mapping logical functions onto the LUTs is presented that exploits the features of the proposed CLB architecture to detect and correct the SEU faults in the LUTs. Experimental results obtained by mapping standard benchmark circuits on the proposed architecture indicate that on an average, 96% of the SEU in the LUTs can be detected without employing any redundancy. Further, by using Duplication with Comparison (DWC) techniques it is shown that 100% of the SEU in the LUTs can be detected for any circuit that is mapped on the proposed architecture; and for the benchmark circuits, on an average, 96% of the SEU in the LUTs can be automatically (without any user intervention or reconfiguration) corrected.",

author = "Sundar, {E. Syam} and Vikram Chandrasekhar and M. Sashikanth and V. Kamakoti and Vijaykrishnan Narayanan",

year = "2004",

month = dec,

day = "1",

language = "English (US)",

isbn = "0780386515",

series = "Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04",

pages = "121--128",

editor = "O. Diessel and J. Williams",

booktitle = "Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04",

note = "2004 IEEE International Conference on Field-Programmable Technology, FPT '04 ; Conference date: 06-12-2004 Through 08-12-2004",

}

Sundar, ES, Chandrasekhar, V, Sashikanth, M, Kamakoti, V & Narayanan, V 2004, A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. in O Diessel & J Williams (eds), Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04, pp. 121-128, 2004 IEEE International Conference on Field-Programmable Technology, FPT '04, Brisbane, Australia, 12/6/04.

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. / Sundar, E. Syam; Chandrasekhar, Vikram; Sashikanth, M. et al.
Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. ed. / O. Diessel; J. Williams. 2004. p. 121-128 (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs

AU - Sundar, E. Syam

AU - Chandrasekhar, Vikram

AU - Sashikanth, M.

AU - Kamakoti, V.

AU - Narayanan, Vijaykrishnan

PY - 2004/12/1

Y1 - 2004/12/1

N2 - This paper proposes a new CLB architecture for FPGAs that can detect and correct Single Event Upset (SEU) faults in the LUTs. A methodology for mapping logical functions onto the LUTs is presented that exploits the features of the proposed CLB architecture to detect and correct the SEU faults in the LUTs. Experimental results obtained by mapping standard benchmark circuits on the proposed architecture indicate that on an average, 96% of the SEU in the LUTs can be detected without employing any redundancy. Further, by using Duplication with Comparison (DWC) techniques it is shown that 100% of the SEU in the LUTs can be detected for any circuit that is mapped on the proposed architecture; and for the benchmark circuits, on an average, 96% of the SEU in the LUTs can be automatically (without any user intervention or reconfiguration) corrected.

AB - This paper proposes a new CLB architecture for FPGAs that can detect and correct Single Event Upset (SEU) faults in the LUTs. A methodology for mapping logical functions onto the LUTs is presented that exploits the features of the proposed CLB architecture to detect and correct the SEU faults in the LUTs. Experimental results obtained by mapping standard benchmark circuits on the proposed architecture indicate that on an average, 96% of the SEU in the LUTs can be detected without employing any redundancy. Further, by using Duplication with Comparison (DWC) techniques it is shown that 100% of the SEU in the LUTs can be detected for any circuit that is mapped on the proposed architecture; and for the benchmark circuits, on an average, 96% of the SEU in the LUTs can be automatically (without any user intervention or reconfiguration) corrected.

UR - http://www.scopus.com/inward/record.url?scp=20844449226&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=20844449226&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:20844449226

SN - 0780386515

T3 - Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

SP - 121

EP - 128

BT - Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

A2 - Diessel, O.

A2 - Williams, J.

T2 - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

Y2 - 6 December 2004 through 8 December 2004

ER -

Sundar ES, Chandrasekhar V, Sashikanth M, Kamakoti V, Narayanan V. A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. In Diessel O, Williams J, editors, Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. 2004. p. 121-128. (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this