A novel dimensionally-decomposed router for on-chip communication in 3D architectures

Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Vijaykrishnan Narayanan, Mazin S. Yousif, Chita R. Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

224 Scopus citations


Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities and burgeoning die sizes in multi-core architectures. Partitioning a larger die into smaller segments and then stacking them in a 3D fashion can significantly reduce latency and energy consumption. Such benefits emanate from the notion that inter-wafer distances are negligible compared to intra-wafer distances. This attribute substantially reduces global wiring length in 3D chips. The work in this paper integrates the increasingly popular idea of packet-based Networks-on-Chip (NoC) into a 3D setting. While NoCs have been studied extensively in the 2D realm, the microarchitectural ramifications of moving into the third dimension have yet to be fully explored. This paper presents a detailed exploration of inter-strata communication architectures in 3D NoCs. Three design options are investigated; a simple bus-based inter-wafer connection, a hop-by-hop standard 3D design, and a full 3D crossbar implementation. In this context, we propose a novel partially-connected 3D crossbar structure, called the 3D Dimensionally- Decomposed (DimDe) Router, which provides a good tradeoff between circuit complexity and performance benefits. Simulation results using (a) a stand-alone cycle-accurate 3D NoC simulator running synthetic workloads, and (b) a hybrid 3D NoC/cache simulation environment running real commercial and scientific benchmarks, indicate that the proposed DimDe design provides latency and throughput improvements of over 20% on average over the other 3D architectures, while remaining within 5% of the full 3D crossbar performance. Furthermore, based on synthesized hardware implementations in 90 nm technology, the DimDe architecture outperforms all other designs - including the full 3D crossbar - by an average of 26% in terms of the Energy-Delay Product (EDP).

Original languageEnglish (US)
Title of host publicationISCA'07
Subtitle of host publication34th Annual International Symposium on Computer Architecture, Conference Proceedings
Number of pages12
StatePublished - 2007
EventISCA'07: 34th Annual International Symposium on Computer Architecture - San Diego, CA, United States
Duration: Jun 9 2007Jun 13 2007

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897


OtherISCA'07: 34th Annual International Symposium on Computer Architecture
Country/TerritoryUnited States
CitySan Diego, CA

All Science Journal Classification (ASJC) codes

  • General Engineering


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