TY - GEN
T1 - A novel low power 6-bit FLASH ADC using charge steering amplifier for RF applications
AU - Movva, Krishna Kumar
AU - Azeemuddin, Syed
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2017/10/10
Y1 - 2017/10/10
N2 - In this paper we present a novel low power 6-bit Flash analog-to-digital converter design using charge steering amplifier for RF applications. The architecture and performance of the designed ADC is described in detail and compared with conventional and other Flash ADCs. The proposed design offers lower power consumption by using a charge-steering amplifier based comparator; the power supply voltage is 0.7 V minimum which makes this design adaptable to wide variety of RF based System-on-Chip (SoC) applications. The ADC is designed in 28nm standard CMOS process with operating sampling frequency of 1GS/s and the performance parameters DNL and INL are ±0.3 LSB and ±0.35 LSB respectively, spurious-free dynamic range (SFDR) is 39 dB, signal-to-noise and distortion ratio (SNDR) is 37.15 dB, effective number of bits (ENOB) is 5.88 bits, power consumption is 3.57 mW @ 0.7 V supply voltage and FOM is 60.6 fJ/conversion-step.
AB - In this paper we present a novel low power 6-bit Flash analog-to-digital converter design using charge steering amplifier for RF applications. The architecture and performance of the designed ADC is described in detail and compared with conventional and other Flash ADCs. The proposed design offers lower power consumption by using a charge-steering amplifier based comparator; the power supply voltage is 0.7 V minimum which makes this design adaptable to wide variety of RF based System-on-Chip (SoC) applications. The ADC is designed in 28nm standard CMOS process with operating sampling frequency of 1GS/s and the performance parameters DNL and INL are ±0.3 LSB and ±0.35 LSB respectively, spurious-free dynamic range (SFDR) is 39 dB, signal-to-noise and distortion ratio (SNDR) is 37.15 dB, effective number of bits (ENOB) is 5.88 bits, power consumption is 3.57 mW @ 0.7 V supply voltage and FOM is 60.6 fJ/conversion-step.
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U2 - 10.1109/ISVDAT.2016.8064904
DO - 10.1109/ISVDAT.2016.8064904
M3 - Conference contribution
AN - SCOPUS:85034780921
T3 - 2016 20th International Symposium on VLSI Design and Test, VDAT 2016
BT - 2016 20th International Symposium on VLSI Design and Test, VDAT 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th International Symposium on VLSI Design and Test, VDAT 2016
Y2 - 24 May 2016 through 27 May 2016
ER -