TY - GEN
T1 - A novel Si-tunnel FET based SRAM design for ultra low-power 0.3V V DD applications
AU - Singh, J.
AU - Ramakrishnan, K.
AU - Mookerjea, S.
AU - Datta, S.
AU - Vijaykrishnan, N.
AU - Pradhan, D.
PY - 2010
Y1 - 2010
N2 - Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6T SRAM cells. To overcome this limitation, 7T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6T SRAM design using Si-TFETs for reliable operation with low leakage at ultra low voltages. We also demonstrate that a functional 6T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using proposed design when compared with the 7T TFET SRAM cell. We achieve a leakage reduction improvement of 700X and 1600X over traditional CMOS SRAM designs at VDD of 0.3V and 0.5V respectively which makes it suitable for use at ultra-low power applications.
AB - Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6T SRAM cells. To overcome this limitation, 7T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6T SRAM design using Si-TFETs for reliable operation with low leakage at ultra low voltages. We also demonstrate that a functional 6T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using proposed design when compared with the 7T TFET SRAM cell. We achieve a leakage reduction improvement of 700X and 1600X over traditional CMOS SRAM designs at VDD of 0.3V and 0.5V respectively which makes it suitable for use at ultra-low power applications.
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U2 - 10.1109/ASPDAC.2010.5419897
DO - 10.1109/ASPDAC.2010.5419897
M3 - Conference contribution
AN - SCOPUS:77951235032
SN - 9781424457656
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 181
EP - 186
BT - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
T2 - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Y2 - 18 January 2010 through 21 January 2010
ER -