TY - GEN
T1 - A novel slope detection technique for robust STTRAM sensing
AU - Motaman, Seyedhamidreza
AU - Ghosh, Swaroop
AU - Kulkarni, Jaydeep P.
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/9/21
Y1 - 2015/9/21
N2 - Spin-Torque-Transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of magnetic tunnel junction (MTJ) and access transistor poses serious challenge to sensing. Nondestructive sensing suffers from reference resistance variation whereas destructive sensing suffers from failures due to unoptimized selection of data and reference currents. We propose a novel slope detection technique to exploit MTJ resistance switching from high to low state using low-overhead sample-and-hold circuit. The proposed sensing technique is destructive in nature and can be combined with double sampling for improved robustness. Simulation results reveal <0.12% failure under process variation using single sampling (at 0.2% area overhead) and <0.08% failures with double sampling (at 0.6% area overhead). The overall sense time is found to be 6.8ns.
AB - Spin-Torque-Transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of magnetic tunnel junction (MTJ) and access transistor poses serious challenge to sensing. Nondestructive sensing suffers from reference resistance variation whereas destructive sensing suffers from failures due to unoptimized selection of data and reference currents. We propose a novel slope detection technique to exploit MTJ resistance switching from high to low state using low-overhead sample-and-hold circuit. The proposed sensing technique is destructive in nature and can be combined with double sampling for improved robustness. Simulation results reveal <0.12% failure under process variation using single sampling (at 0.2% area overhead) and <0.08% failures with double sampling (at 0.6% area overhead). The overall sense time is found to be 6.8ns.
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U2 - 10.1109/ISLPED.2015.7273482
DO - 10.1109/ISLPED.2015.7273482
M3 - Conference contribution
AN - SCOPUS:84958527352
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 7
EP - 12
BT - Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015
Y2 - 22 July 2015 through 24 July 2015
ER -