TY - GEN
T1 - A novel threshold voltage defined switch for circuit camouflaging
AU - Nirmala, Ithihasa Reddy
AU - Vontela, Deepak
AU - Ghosh, Swaroop
AU - Iyengar, Anirudh
N1 - Funding Information:
This work is supported by Defense Advanced Research Projects Agency under award #D15AP00089
Publisher Copyright:
© 2016 IEEE.
PY - 2016/7/22
Y1 - 2016/7/22
N2 - Semiconductor supply chain is increasingly getting exposed to variety of security attacks such as Trojan insertion, cloning, counterfeiting, reverse engineering (RE), piracy of Intellectual Property (IP) or Integrated Circuit (IC) and side-channel analysis due to involvement of untrusted parties. In this paper, we propose threshold voltage-defined switches that will camouflage the logic gate both logically and physically to resist RE and IP piracy. The proposed gate can function as NAND, AND, NOR, OR, XOR, and XNOR robustly using threshold defined switches. We also propose a flavor of camouflaged gate that represents reduced functionality (NAND, NOR and NOT) at much lower overhead. The camouflaged design operates at nominal voltage and obeys conventional reliability limits. A small fraction of gates can be camouflaged to increase the RE effort extremely high. Simulation results indicate 46-53% area, 59-68% delay and 52-76% power overhead when 5-15% gates are identified and camouflaged using the proposed gate. A significant higher RE effort is achieved when the proposed gate is employed in the netlist using controllability, observability and hamming distance sensitivity based gate selection metrics.
AB - Semiconductor supply chain is increasingly getting exposed to variety of security attacks such as Trojan insertion, cloning, counterfeiting, reverse engineering (RE), piracy of Intellectual Property (IP) or Integrated Circuit (IC) and side-channel analysis due to involvement of untrusted parties. In this paper, we propose threshold voltage-defined switches that will camouflage the logic gate both logically and physically to resist RE and IP piracy. The proposed gate can function as NAND, AND, NOR, OR, XOR, and XNOR robustly using threshold defined switches. We also propose a flavor of camouflaged gate that represents reduced functionality (NAND, NOR and NOT) at much lower overhead. The camouflaged design operates at nominal voltage and obeys conventional reliability limits. A small fraction of gates can be camouflaged to increase the RE effort extremely high. Simulation results indicate 46-53% area, 59-68% delay and 52-76% power overhead when 5-15% gates are identified and camouflaged using the proposed gate. A significant higher RE effort is achieved when the proposed gate is employed in the netlist using controllability, observability and hamming distance sensitivity based gate selection metrics.
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U2 - 10.1109/ETS.2016.7519286
DO - 10.1109/ETS.2016.7519286
M3 - Conference contribution
AN - SCOPUS:84991516831
T3 - Proceedings of the European Test Workshop
BT - Proceedings - 2016 21st IEEE European Test Symposium, ETS 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st IEEE European Test Symposium, ETS 2016
Y2 - 23 May 2016 through 26 May 2016
ER -