A parallel architecture for hardware face detection

T. Theocharides; N. Vijaykrishnan; M. J. Irwin

doi:10.1109/ISVLSI.2006.10

A parallel architecture for hardware face detection

T. Theocharides, N. Vijaykrishnan, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

58 Scopus citations

Abstract

Face detection is a very important application in the field of machine vision. In this paper, we present a scalable parallel architecture which performs face detection using the AdaBoost algorithm. Experimental results show that the proposed architecture can detect faces with the same accuracy as the software implementation, on real-time video at a frame rate of 52 frames per second.

Original language	English (US)
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Pages	452-453
Number of pages	2
DOIs	https://doi.org/10.1109/ISVLSI.2006.10
State	Published - 2006
Event	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 - Klarlsruhe, Germany Duration: Mar 2 2006 → Mar 3 2006

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Volume	2006

Other

Other	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Country/Territory	Germany
City	Klarlsruhe
Period	3/2/06 → 3/3/06

All Science Journal Classification (ASJC) codes

General Engineering

Access to Document

10.1109/ISVLSI.2006.10

Cite this

Theocharides, T., Vijaykrishnan, N., & Irwin, M. J. (2006). A parallel architecture for hardware face detection. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 (pp. 452-453). Article 1602492 (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006; Vol. 2006). https://doi.org/10.1109/ISVLSI.2006.10

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title = "A parallel architecture for hardware face detection",

abstract = "Face detection is a very important application in the field of machine vision. In this paper, we present a scalable parallel architecture which performs face detection using the AdaBoost algorithm. Experimental results show that the proposed architecture can detect faces with the same accuracy as the software implementation, on real-time video at a frame rate of 52 frames per second.",

author = "T. Theocharides and N. Vijaykrishnan and Irwin, {M. J.}",

year = "2006",

doi = "10.1109/ISVLSI.2006.10",

language = "English (US)",

isbn = "0769525334",

series = "Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006",

pages = "452--453",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006",

note = "IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 ; Conference date: 02-03-2006 Through 03-03-2006",

}

Theocharides, T, Vijaykrishnan, N & Irwin, MJ 2006, A parallel architecture for hardware face detection. in Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006., 1602492, Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, vol. 2006, pp. 452-453, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, Klarlsruhe, Germany, 3/2/06. https://doi.org/10.1109/ISVLSI.2006.10

A parallel architecture for hardware face detection. / Theocharides, T.; Vijaykrishnan, N.; Irwin, M. J.
Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. 2006. p. 452-453 1602492 (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Face detection is a very important application in the field of machine vision. In this paper, we present a scalable parallel architecture which performs face detection using the AdaBoost algorithm. Experimental results show that the proposed architecture can detect faces with the same accuracy as the software implementation, on real-time video at a frame rate of 52 frames per second.

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A parallel architecture for hardware face detection

Abstract

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Other

All Science Journal Classification (ASJC) codes

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