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A parallel architecture for secure FPGA symmetric encryption
E. J. Swankoski
, R. R. Brooks
,
V. Narayanan
,
M. Kandemir
, M. J. Irwin
School of Electrical Engineering and Computer Science
Institute for Computational and Data Sciences (ICDS)
Computer Science and Engineering
Research output
:
Chapter in Book/Report/Conference proceeding
›
Conference contribution
21
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Scopus citations
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Keyphrases
Parallel Architecture
100%
Symmetric Encryption
100%
Encryption
50%
High Performance
25%
Hardware Function
25%
Physical Separation
25%
Hardware Efficiency
25%
Duplication
25%
System Throughput
25%
Physical Resources
25%
Multiple Users
25%
Security Design
25%
Pipelined Architecture
25%
Performance-based
25%
DES Algorithm
25%
Financial Transactions
25%
Physical Security
25%
Computing Platform
25%
AES Algorithm
25%
Reconfigurable Computing
25%
High-performance Architecture
25%
Spatial Isolation
25%
Temporal Isolation
25%
Cryptographic Primitives
25%
Cryptographic Algorithms
25%
Parallel Encryption
25%
Random Function
25%
Encryption System
25%
3DES Algorithm
25%
Loop Unrolling
25%
Fully Transient
25%
Key Storage
25%
Secure System
25%
Single Blocks
25%
Physical Attack
25%
Computer Science
Parallel Architectures
100%
Symmetric Encryption
100%
Field Programmable Gate Arrays
100%
Cryptography
75%
Input/Output
25%
Physical Resource
25%
Security Design
25%
pipelined architecture
25%
Data Encryption
25%
Computing Platform
25%
Secure Environment
25%
Physical Separation
25%
reconfigurable computing
25%
Physical Attack
25%
Cryptographic Algorithm
25%
Cryptographic Primitive
25%
Encryption System
25%
Advanced Encryption Standard
25%
Temporal Isolation
25%
Random Function
25%