A power-efficient hybrid architecture design for image recognition using CNNs

Jinhang Choi; Srivatsa Srinivasa; Yasuki Tanabe; Jack Sampson; Vijaykrishnan Narayanan

doi:10.1109/ISVLSI.2018.00015

A power-efficient hybrid architecture design for image recognition using CNNs

Jinhang Choi, Srivatsa Srinivasa, Yasuki Tanabe, Jack Sampson, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Convolutional Neural Networks (CNNs) are proving to be highly effective in vision recognition systems. However, it is a challenge to use them in real-Time embedded systems because of their requirements for computation-intensive operations and high memory bandwidth. This paper proposes a power-efficient CNN architecture that has a pipelined streaming accelerator coupled to 4,096 SIMD Processing Elements. We reduce memory bandwidth via hierarchical intermediate data buffering and batch processing on the chip. As a result, we achieve high power-efficiency: Our proposed design processes 2,175 regions/second when operating at 500MHz with a power budget less than 7.5 Watts.

Original language	English (US)
Title of host publication	Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
Publisher	IEEE Computer Society
Pages	22-27
Number of pages	6
ISBN (Print)	9781538670996
DOIs	https://doi.org/10.1109/ISVLSI.2018.00015
State	Published - Aug 7 2018
Event	17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018 - Hong Kong, Hong Kong Duration: Jul 9 2018 → Jul 11 2018

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2018-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Other

Other	17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
Country/Territory	Hong Kong
City	Hong Kong
Period	7/9/18 → 7/11/18

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2018.00015

Cite this

Choi, J., Srinivasa, S., Tanabe, Y., Sampson, J., & Narayanan, V. (2018). A power-efficient hybrid architecture design for image recognition using CNNs. In Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018 (pp. 22-27). Article 8429336 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2018-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2018.00015

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title = "A power-efficient hybrid architecture design for image recognition using CNNs",

abstract = "Convolutional Neural Networks (CNNs) are proving to be highly effective in vision recognition systems. However, it is a challenge to use them in real-Time embedded systems because of their requirements for computation-intensive operations and high memory bandwidth. This paper proposes a power-efficient CNN architecture that has a pipelined streaming accelerator coupled to 4,096 SIMD Processing Elements. We reduce memory bandwidth via hierarchical intermediate data buffering and batch processing on the chip. As a result, we achieve high power-efficiency: Our proposed design processes 2,175 regions/second when operating at 500MHz with a power budget less than 7.5 Watts.",

author = "Jinhang Choi and Srivatsa Srinivasa and Yasuki Tanabe and Jack Sampson and Vijaykrishnan Narayanan",

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year = "2018",

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doi = "10.1109/ISVLSI.2018.00015",

language = "English (US)",

isbn = "9781538670996",

series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",

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Choi, J, Srinivasa, S, Tanabe, Y, Sampson, J & Narayanan, V 2018, A power-efficient hybrid architecture design for image recognition using CNNs. in Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018., 8429336, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2018-July, IEEE Computer Society, pp. 22-27, 17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, Hong Kong, 7/9/18. https://doi.org/10.1109/ISVLSI.2018.00015

A power-efficient hybrid architecture design for image recognition using CNNs. / Choi, Jinhang; Srinivasa, Srivatsa; Tanabe, Yasuki et al.
Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018. IEEE Computer Society, 2018. p. 22-27 8429336 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2018-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A power-efficient hybrid architecture design for image recognition using CNNs

AU - Choi, Jinhang

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AU - Sampson, Jack

AU - Narayanan, Vijaykrishnan

PY - 2018/8/7

Y1 - 2018/8/7

N2 - Convolutional Neural Networks (CNNs) are proving to be highly effective in vision recognition systems. However, it is a challenge to use them in real-Time embedded systems because of their requirements for computation-intensive operations and high memory bandwidth. This paper proposes a power-efficient CNN architecture that has a pipelined streaming accelerator coupled to 4,096 SIMD Processing Elements. We reduce memory bandwidth via hierarchical intermediate data buffering and batch processing on the chip. As a result, we achieve high power-efficiency: Our proposed design processes 2,175 regions/second when operating at 500MHz with a power budget less than 7.5 Watts.

AB - Convolutional Neural Networks (CNNs) are proving to be highly effective in vision recognition systems. However, it is a challenge to use them in real-Time embedded systems because of their requirements for computation-intensive operations and high memory bandwidth. This paper proposes a power-efficient CNN architecture that has a pipelined streaming accelerator coupled to 4,096 SIMD Processing Elements. We reduce memory bandwidth via hierarchical intermediate data buffering and batch processing on the chip. As a result, we achieve high power-efficiency: Our proposed design processes 2,175 regions/second when operating at 500MHz with a power budget less than 7.5 Watts.

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A power-efficient hybrid architecture design for image recognition using CNNs

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