A process scheduler-based approach to NoC power management

Increasing use of on-chip networks as communication infrastructure in both high performance and low end computing makes it important to consider their power consumption. Several previously proposed approaches to power management in the context of NoCs (network-on-chips) are either pure hardware based or focus exclusively on a single application execution scenario. This paper makes two major contributions. First, it proposes a software-based proactive on-chip network power management scheme that operates under a given process scheduler. Second, it presents a power-aware process scheduling strategy, with the goal of maximizing power savings when we have multiple applications in the system. The paper also evaluates the proposed schemes under the different execution scenarios in the context of NoCs based on a two-dimensional mesh topology and compares them to each other as well as to a previouslyproposed hardware-based network power management scheme. Our experimental evaluation using six data-intensive applications shows that the proposed software based approach is competitive with the hardware based scheme. Also, we found that the power aware scheduling brings significant energy savings.