A scalable bandwidth aware architecture for connected component labeling

Vikram Sampath Kumar; Kevin Irick; Ahmed Al Maashri; Vijaykrishnan Narayanan

doi:10.1109/ISVLSI.2010.89

A scalable bandwidth aware architecture for connected component labeling

Vikram Sampath Kumar
, Kevin Irick
, Ahmed Al Maashri
, Vijaykrishnan Narayanan

Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Scopus citations

Abstract

Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component Labeling architecture that includes a scalable processor that can be tuned to match the I/O bandwidth available in modern embedded computing platforms.

Original language	English (US)
Title of host publication	Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
Pages	116-121
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2010.89
State	Published - 2010
Event	IEEE Annual Symposium on VLSI, ISVLSI 2010 - Lixouri, Kefalonia, Greece Duration: Jul 5 2010 → Jul 7 2010

Other

Other	IEEE Annual Symposium on VLSI, ISVLSI 2010
Country/Territory	Greece
City	Lixouri, Kefalonia
Period	7/5/10 → 7/7/10

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2010.89

Cite this

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title = "A scalable bandwidth aware architecture for connected component labeling",

abstract = "Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component Labeling architecture that includes a scalable processor that can be tuned to match the I/O bandwidth available in modern embedded computing platforms.",

author = "Kumar, \{Vikram Sampath\} and Kevin Irick and Maashri, \{Ahmed Al\} and Vijaykrishnan Narayanan",

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language = "English (US)",

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AU - Irick, Kevin

AU - Maashri, Ahmed Al

AU - Narayanan, Vijaykrishnan

PY - 2010

Y1 - 2010

N2 - Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component Labeling architecture that includes a scalable processor that can be tuned to match the I/O bandwidth available in modern embedded computing platforms.

AB - Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component Labeling architecture that includes a scalable processor that can be tuned to match the I/O bandwidth available in modern embedded computing platforms.

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U2 - 10.1109/ISVLSI.2010.89

DO - 10.1109/ISVLSI.2010.89

M3 - Conference contribution

AN - SCOPUS:77957958536

SN - 9780769540764

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BT - Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010

T2 - IEEE Annual Symposium on VLSI, ISVLSI 2010

Y2 - 5 July 2010 through 7 July 2010

ER -

A scalable bandwidth aware architecture for connected component labeling

Abstract

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All Science Journal Classification (ASJC) codes

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