TY - GEN
T1 - A self-testable SiGe LNA and built-in-self-test methodology for multiple performance specifications of RF amplifiers
AU - Goyal, Abhilash
AU - Swaminathan, Madhavan
AU - Chatterjee, Abhijit
AU - Howard, Duane
AU - Cressler, John D.
PY - 2012
Y1 - 2012
N2 - In this paper, a self-testable SiGe low noise amplifier (LNA) is designed and a Built-in-Self-Test (BIST) methodology is proposed for amplifiers embedded in RF systems. In this BIST methodology, the RF amplifier has the capability to simultaneously test multiple performance specifications on-chip, including Gain and PldB. The self-testable LNA can be placed in a testing mode, in which it self generates a signature of its health using oscillation principles. It eliminates the requirement of any external test stimulus for testing purposes, thus enables the possibility of self-testable RF designs. For the proof of concept, the presented SiGe LNA is designed to operate in the X-band (9.0 GHz) in a commercially-available 6 metal layer, 0.18 μm, 120 GHz SiGe BiCMOS platform. This self-testing design concept can be extended to CMOS amplifiers as well. Furthermore, in this paper, the built-in-self-test methodology is demonstrated using board-level as well as chip-level prototypes.
AB - In this paper, a self-testable SiGe low noise amplifier (LNA) is designed and a Built-in-Self-Test (BIST) methodology is proposed for amplifiers embedded in RF systems. In this BIST methodology, the RF amplifier has the capability to simultaneously test multiple performance specifications on-chip, including Gain and PldB. The self-testable LNA can be placed in a testing mode, in which it self generates a signature of its health using oscillation principles. It eliminates the requirement of any external test stimulus for testing purposes, thus enables the possibility of self-testable RF designs. For the proof of concept, the presented SiGe LNA is designed to operate in the X-band (9.0 GHz) in a commercially-available 6 metal layer, 0.18 μm, 120 GHz SiGe BiCMOS platform. This self-testing design concept can be extended to CMOS amplifiers as well. Furthermore, in this paper, the built-in-self-test methodology is demonstrated using board-level as well as chip-level prototypes.
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U2 - 10.1109/ISQED.2012.6187467
DO - 10.1109/ISQED.2012.6187467
M3 - Conference contribution
AN - SCOPUS:84863658766
SN - 9781467310369
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 7
EP - 12
BT - Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012
T2 - 13th International Symposium on Quality Electronic Design, ISQED 2012
Y2 - 19 March 2012 through 21 March 2012
ER -